公开(公告)号：US11664297B2

公开(公告)日：2023-05-30

申请号：US17398086

申请日：2021-08-10

Applicant: LBSEMICON CO., LTD.

Inventor： Jae Jin Kwon

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L23/488 ,  H01L23/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11312 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13147 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13116 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.

公开(公告)号：US20190198374A1

公开(公告)日：2019-06-27

申请号：US16293099

申请日：2019-03-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Darrell D. TRUHITTE ,  James P. LETTERMAN, JR.

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27418 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/276 ,  H01L2224/279 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75755 ,  H01L2224/75756 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81856 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83856 ,  H01L2224/85005 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92147 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207

Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

公开(公告)号：US20180174989A1

公开(公告)日：2018-06-21

申请号：US15565904

申请日：2016-03-01

Applicant: JSR CORPORATION

Inventor： JUN MUKAWA ,  SEIICHIROU TAKAHASHI ,  KOUICHI HASEGAWA ,  SHIROU KUSUMOTO

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/1131 ,  H01L2224/11312 ,  H01L2224/1147 ,  H01L2224/11618 ,  H01L2224/11622 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81002 ,  H01L2224/81203 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: The present disclosure relates to a production process for a solder electrode, including a step (1) of forming a coating film of a photosensitive resin composition on a substrate having an electrode pad; a step (2) of forming resist having an opening in a region corresponding to the electrode pad by selectively exposing the coating film to light and further developing the film; a step (3) of heating and/or exposing the resist to light; and a step (4) of filling the opening with molten solder while heating the solder. According to the production process for the solder electrode of the present disclosure, development of cracks on a resist surface can be prevented, and solder filling capability can be improved, even when the resist receives high heat during solder filling as in an IMS method, and therefore the solder electrode adapted for the purpose can be appropriately produced.

公开(公告)号：US09941230B2

公开(公告)日：2018-04-10

申请号：US14985009

申请日：2015-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keiji Matsumoto ,  Keishi Okamoto ,  Yasumitsu K. Orii ,  Kazushige Toriyama

IPC: H01L23/00 ,  G02B6/42

CPC classification number: H01L24/13 ,  G02B6/4219 ,  G02B6/4232 ,  G02B6/4274 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11312 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides an electrical connecting structure between a substrate 21 and a semiconductor chip 22. The electrical connecting structure comprises a metal bump 26 formed on a contact pad 28 of a semiconductor chip 22 and a coating layer 25 formed on the metal bump 26 of the semiconductor chip 22. The coating layer includes material not wettable with solder. The electrical connecting structure further comprises a metal pad 24 formed on the substrate 21. The electrical connecting structure further comprises a solder 29 connecting to a side surface of the metal bump 26 and an outer surface of the metal pad 24. The outer surface is not covered by the coating layer 25.

公开(公告)号：US20170260045A1

公开(公告)日：2017-09-14

申请号：US15529619

申请日：2015-04-01

Applicant: Goertek.Inc

Inventor： Quanbo Zou ,  Zhe Wang

IPC: B81C1/00

CPC classification number: B81C1/00896 ,  B81C2201/0194 ,  B81C2203/01 ,  B81C2203/0127 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/11312 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A transfer method, manufacturing method, device and electronic apparatus of MEMS. The method for MEMS transfer, comprising: depositing a laser-absorbing layer on a first surface of a laser-transparent carrier; forming a MEMS structure on the laser-absorbing layer; attaching the MEMS structure to a receiver; and performing a laser lift-off from the side of the carrier, to remove the carrier. A transfer of high-quality MEMS structure can be achieved in a simple, low cost manner.

公开(公告)号：US20170084566A1

公开(公告)日：2017-03-23

申请号：US15353362

申请日：2016-11-16

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Shinya KIYONO ,  Yoshiaki SATAKE

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H05K3/34 ,  H05K1/18

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/11312 ,  H01L2224/11318 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/11505 ,  H01L2224/11515 ,  H01L2224/13017 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1411 ,  H01L2224/16052 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17104 ,  H01L2224/17107 ,  H01L2224/73204 ,  H01L2224/8112 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81439 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/3025 ,  H01L2924/3841 ,  H05K1/181 ,  H05K3/341 ,  H05K3/3457 ,  H05K13/0465 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.

公开(公告)号：US09516749B2

公开(公告)日：2016-12-06

申请号：US14412395

申请日：2013-02-21

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yoshiyuki Wada ,  Tadahiko Sakai ,  Koji Motomura

IPC: H05K7/00 ,  H05K1/09 ,  H01L23/14 ,  H01L23/498 ,  H05K3/32 ,  H01L23/00 ,  G06K19/077 ,  H01L21/48 ,  H01L25/065 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/12 ,  G02F1/13

CPC classification number: H05K1/097 ,  G02F1/1303 ,  G06K19/07718 ,  G06K19/07745 ,  H01L21/4853 ,  H01L23/145 ,  H01L23/4985 ,  H01L23/49855 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0652 ,  H01L2223/6677 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/13008 ,  H01L2224/13016 ,  H01L2224/13019 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/13301 ,  H01L2224/13311 ,  H01L2224/13318 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13364 ,  H01L2224/13369 ,  H01L2224/1339 ,  H01L2224/1349 ,  H01L2224/13644 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17106 ,  H01L2224/73204 ,  H01L2224/7526 ,  H01L2224/75262 ,  H01L2224/7565 ,  H01L2224/75651 ,  H01L2224/75702 ,  H01L2224/7598 ,  H01L2224/81127 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8159 ,  H01L2224/81601 ,  H01L2224/81611 ,  H01L2224/81618 ,  H01L2224/81624 ,  H01L2224/81639 ,  H01L2224/81644 ,  H01L2224/81647 ,  H01L2224/81655 ,  H01L2224/81657 ,  H01L2224/8166 ,  H01L2224/81664 ,  H01L2224/81669 ,  H01L2224/81815 ,  H01L2224/8184 ,  H01L2224/81871 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/19105 ,  H05K1/0274 ,  H05K1/0313 ,  H05K1/181 ,  H05K3/12 ,  H05K3/321 ,  H05K2201/0108 ,  H05K2201/10674 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01048 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00

Abstract: Disclosed is an electronic component-mounted structure including: a substrate, a conductive wiring pattern formed on a surface of the substrate, and an electronic component having an external terminal and being placed on the surface of the substrate at a mounting position including a terminal joint position of the conductive wiring pattern. The external terminal is joined to the conductive wiring pattern at the terminal joint position such that the external terminal is embedded in the conductive wiring pattern. Therefore, the junction between the external terminal and the conductive wiring pattern can have a high strength as compared with that obtained by joining the external terminal of the electronic component to the conductive wiring pattern merely on the surface of the conductive wiring pattern.

Abstract translation: 公开了一种电子部件安装结构，包括：基板，形成在基板的表面上的导电布线图案和具有外部端子的电子部件，并且在包括端子接头的安装位置处放置在基板的表面上 导电布线图案的位置。 外部端子在端子接合位置处连接到导电布线图案，使得外部端子嵌入导电布线图案中。 因此，与仅将导电布线图案的表面上的电子部件的外部端子与导体布线图案接合而得到的外部端子与导电布线图案的接合部可以具有高的强度。

公开(公告)号：US09508594B2

公开(公告)日：2016-11-29

申请号：US14930984

申请日：2015-11-03

Applicant: International Business Machines Corporation

Inventor： Toyohiro Aoki ,  Hiroyuki Mori ,  Kazushige Toriyama

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  B23K3/06 ,  H01L23/488 ,  H01L23/48

CPC classification number: H01L24/13 ,  B23K3/0623 ,  H01L21/4867 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/34 ,  H01L23/345 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/11013 ,  H01L2224/1131 ,  H01L2224/11312 ,  H01L2224/11416 ,  H01L2224/1148 ,  H01L2224/11618 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17519 ,  H01L2224/27 ,  H01L2224/27416 ,  H01L2224/27515 ,  H01L2224/27618 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29076 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01026 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

公开(公告)号：US09488853B2

公开(公告)日：2016-11-08

申请号：US14678198

申请日：2015-04-03

Applicant: Verily Life Sciences LLC

Inventor： James Etzkorn

IPC: H01L21/768 ,  G02C11/00 ,  H01L23/48 ,  H01L21/56 ,  G02C7/04 ,  H01L23/00 ,  H01L23/528 ,  B29D11/00 ,  H01L23/31

CPC classification number: G02C11/10 ,  A61B5/6821 ,  A61B2562/12 ,  B29D11/00048 ,  B29D11/00807 ,  G02C7/04 ,  G02C7/049 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/08225 ,  H01L2224/11312 ,  H01L2224/13109 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8012 ,  H01L2224/8085 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00 ,  H01L2224/83104 ,  H01L2224/05599 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/00013 ,  H01L2924/20105 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A contact lens having a thin silicon chip integrated therein is provided along with methods for assembling the silicon chip within the contact lens. In an aspect, a method includes creating a plurality of lens contact pads on a lens substrate and creating a plurality of chip contact pads on a chip. The method further involves applying assembly bonding material to the each of the plurality of lens contact pads or chip contact pads, aligning the plurality of lens contact pads with the plurality of chip contact pads, bonding the chip to the lens substrate via the assembly bonding material using flip chip bonding, and forming a contact lens with the lens substrate.

Abstract translation: 集成有薄硅芯片的隐形眼镜与隐形眼镜中的硅芯片的组装方法一起提供。 一方面，一种方法包括在透镜基板上形成多个透镜接触焊盘并在芯片上产生多个芯片接触焊盘。 该方法还包括将组装接合材料施加到多个透镜接触焊盘或芯片接触焊盘中的每一个上，将多个透镜接触焊盘与多个芯片接触焊盘对准，通过组装接合材料将芯片粘合到透镜基板 使用倒装芯片接合，并且与透镜基板形成隐形眼镜。

公开(公告)号：US09478509B2

公开(公告)日：2016-10-25

申请号：US14198711

申请日：2014-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/08145 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2224/034

Abstract: The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Abstract translation: 本发明一般涉及倒装芯片技术，更具体地说，涉及用于在半导体结构上制造机械锚定的控制崩溃芯片连接（C 4）焊盘的方法和结构。 在一个实施例中，公开了一种方法，其可以包括形成具有延伸到半导体结构中的一个或多个锚定区域的焊盘，并且可能在温度波动期间阻止焊盘与TSV物理分离。