公开(公告)号：US10770407B2

公开(公告)日：2020-09-08

申请号：US16240436

申请日：2019-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhuojie Wu ,  Cathryn J. Christiansen ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald G. Filippi, Jr. ,  Eric D. Hunt-Schroeder ,  Nicholas A. Polomoff

IPC: H01L23/00 ,  H01L23/538 ,  G01N27/12

Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

公开(公告)号：US20200219826A1

公开(公告)日：2020-07-09

申请号：US16240436

申请日：2019-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhuojie Wu ,  Cathryn J. Christiansen ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald G. Filippi, JR. ,  Eric D. Hunt-Schroeder ,  Nicholas A. Polomoff

IPC: H01L23/00 ,  G01N27/12 ,  H01L23/538

Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

公开(公告)号：US20190123005A1

公开(公告)日：2019-04-25

申请号：US15793130

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald Gene Filippi, JR.

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/308

CPC classification number: H01L24/05 ,  H01L21/3081 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/0556 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462

Abstract: The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.

公开(公告)号：US09997456B2

公开(公告)日：2018-06-12

申请号：US15220764

申请日：2016-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Atsushi Ogino

IPC: H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/48 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/5286

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

公开(公告)号：US09947602B2

公开(公告)日：2018-04-17

申请号：US15237066

申请日：2016-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhuojie Wu ,  Erdem Kaltalioglu

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L22/14 ,  H01L22/32 ,  H01L23/585 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3512

Abstract: A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a first conductive structure disposed proximate a perimeter of the IC structure; and a second conductive structure disposed parallel to the first conductive structure and proximate the perimeter of the IC structure. The sensor also includes a set of interdigitating conductive elements including a first plurality of conductive elements electrically coupled to the first conductive structure interdigitating with a second plurality of conductive elements electrically coupled to the second conductive structure.

公开(公告)号：US09768065B1

公开(公告)日：2017-09-19

申请号：US15203084

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ping-Chuan Wang ,  Erdem Kaltalioglu ,  Ronald G. Filippi ,  Cathryn J. Christiansen

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76873 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53233 ,  H01L23/53238

Abstract: Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.

公开(公告)号：US09478509B2

公开(公告)日：2016-10-25

申请号：US14198711

申请日：2014-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/08145 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2224/034

Abstract: The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Abstract translation: 本发明一般涉及倒装芯片技术，更具体地说，涉及用于在半导体结构上制造机械锚定的控制崩溃芯片连接（C 4）焊盘的方法和结构。 在一个实施例中，公开了一种方法，其可以包括形成具有延伸到半导体结构中的一个或多个锚定区域的焊盘，并且可能在温度波动期间阻止焊盘与TSV物理分离。

公开(公告)号：US10438890B2

公开(公告)日：2019-10-08

申请号：US15976300

申请日：2018-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Atsushi Ogino

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/283 ,  H01L21/28

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

公开(公告)号：US20190027433A1

公开(公告)日：2019-01-24

申请号：US15652594

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erdem Kaltalioglu ,  Ronald G. Filippi, JR. ,  Ping-Chuan Wang ,  Cathryn Christiansen

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768

Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.

公开(公告)号：US20180033718A1

公开(公告)日：2018-02-01

申请号：US15220764

申请日：2016-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Atsushi Ogino

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/528 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/48 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/5286

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.