公开(公告)号：US20240363407A1

公开(公告)日：2024-10-31

申请号：US18309669

申请日：2023-04-28

申请人： Applied Materials, Inc.

发明人： Jie ZHANG ,  Liqi WU ,  Cory LAFOLLETT ,  Tsung-Han YANG ,  Wei WENG ,  Qihao ZHU ,  Jiang LU ,  Rongjun WANG ,  Xianmin TANG

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76877 ,  H01L21/02274 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76883

摘要： Embodiments of the present disclosure generally relate to a method for forming an electrically conductive feature on a substrate. In one embodiment, the method includes forming a first conductive layer via physical vapor deposition (PVD) in an opening of a substrate. The first conductive layer has a thickness of less than 20 angstroms. The method further includes forming a second conductive layer via PVD on the first conductive layer. The first conductive layer and the second conductive layer are formed at a temperature of less than 50° C. The method further includes annealing at least a portion of the first conductive layer and the second conductive layer.

公开(公告)号：US20240321795A1

公开(公告)日：2024-09-26

申请号：US18603113

申请日：2024-03-12

申请人： STMicroelectronics International N.V.

发明人： Olivier ORY ,  Michael DE CRUZ

IPC分类号： H01L23/00 ,  H01L21/288 ,  H01L21/463 ,  H01L21/768 ,  H05K1/18

CPC分类号： H01L24/13 ,  H01L21/288 ,  H01L21/463 ,  H01L21/76865 ,  H01L24/29 ,  H01L24/73 ,  H05K1/181 ,  H01L2224/13007 ,  H01L2224/13025 ,  H01L2224/29005 ,  H01L2224/2919 ,  H01L2224/73153 ,  H01L2924/01029

摘要： The present disclosure relates to a method of manufacturing first electronic components, each comprising a second electronic component, each second component comprising at least two contact metallizations, the method comprising: a) forming, on a substrate, at least two metal pillars; b) forming, over a portion of the surface of each pillar, a metallization of the component; c) covering the surface of the substrate, the pillars, and the metallizations of the first components with a first resin layer; d) removing the substrate to expose a surface of the pillars, opposite to the metallizations of the components; e) bonding and electrically connecting the second components, by their metallizations, to the surface of the pillars opposite to the metallizations of the first components; and f) expose the surface of the metallizations of the first components opposite to the pillars.

公开(公告)号：US12074062B2

公开(公告)日：2024-08-27

申请号：US17373914

申请日：2021-07-13

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Taoyan Yan

IPC分类号： H01L21/768 ,  H01L21/285

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76889 ,  H01L21/76895

摘要： Some examples of this disclosure relate to the field of the semiconductor technology, and disclose a method for manufacturing a semiconductor structure. The method for manufacturing of the semiconductor structure includes: providing a base, wherein the base includes a metal layer and an oxide located in the metal layer or on a surface of the metal layer; and performing heat treatment on the base, wherein a reducing gas is introduced during the heat treatment, and the metal layer is converted into a metal compound layer after the heat treatment. This disclosure can improve the performance of the semiconductor structure.

公开(公告)号：US20240282627A1

公开(公告)日：2024-08-22

申请号：US18629122

申请日：2024-04-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Peng-Soon LIM ,  Chung-Liang Cheng ,  Huang-Lin Chao

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088

CPC分类号： H01L21/76871 ,  H01L21/76804 ,  H01L21/76865 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/088 ,  H01L21/76843 ,  H01L21/823412 ,  H01L21/823456

摘要： A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.

公开(公告)号：US20240162154A1

公开(公告)日：2024-05-16

申请号：US18054637

申请日：2022-11-11

申请人： MICRON TECHNOLOGY, INC.

发明人： KEIICHI TSUCHIYA ,  KEIZO KAWAKITA

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/535 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266

摘要： An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction crossing the first direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. A maximum width of the upper conductive section in the first direction is smaller than a maximum width of the lower conductive section in the first direction.

公开(公告)号：US20240162084A1

公开(公告)日：2024-05-16

申请号：US18424246

申请日：2024-01-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsin-Yen HUANG ,  Ting-Ya LO ,  Shao-Kuan LEE ,  Chi-Lin TENG ,  Cheng-Chin LEE ,  Shau-Lin SHUE ,  Hsiao-Kang CHANG

IPC分类号： H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/02167

摘要： A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

公开(公告)号：US11978661B2

公开(公告)日：2024-05-07

申请号：US17118697

申请日：2020-12-11

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Fuad H. Al-Amoody ,  Felix P. Anderson ,  Spencer H. Porter ,  Mark D. Levy ,  Siva P. Adusumilli

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76865 ,  H01L23/5226 ,  H01L29/41725 ,  H01L23/5283 ,  H01L23/53295

摘要： Disclosed is a structure with ultralow-K (ULK) dielectric-gap wrapped contact(s). The structure includes an opening, which extends through a dielectric layer and is aligned above a device. A contact is within the opening and electrically connected to the device. Instead of the contact completely filling the opening, a ULK dielectric-gap (e.g., an air or gas-filled gap or a void) at least partially separates the contact from the sidewall(s) of the contact opening and further wraps laterally around the contact. Also disclosed is a method for forming the structure and, particularly, for forming a ULK dielectric-gap by etching back an exposed top end of an adhesive layer initially lining a contact opening to form a gap between the sidewall(s) of the opening and the contact and then capping the gap with an additional dielectric layer such that the gap is filled with air or gas or is under vacuum.

公开(公告)号：US11923243B2

公开(公告)日：2024-03-05

申请号：US17460628

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Shau-Lin Shue ,  Hsiao-Kang Chang

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/02167 ,  H01L21/30617

摘要： A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

公开(公告)号：US20240071816A1

公开(公告)日：2024-02-29

申请号：US17896919

申请日：2022-08-26

申请人： Micron Technology, Inc.

发明人： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11573

CPC分类号： H01L21/76816 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11573

摘要： Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.

公开(公告)号：US11862513B2

公开(公告)日：2024-01-02

申请号：US17449555

申请日：2021-09-30

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Xifei Bao

IPC分类号： H01L21/768 ,  H10B12/00

CPC分类号： H01L21/7681 ,  H01L21/7688 ,  H01L21/76843 ,  H01L21/76865 ,  H10B12/02

摘要： A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided. A barrier layer is formed on the substrate. A sacrificial layer is formed on the barrier layer. An opening pattern is formed over the sacrificial layer by utilizing a photolithography process. The sacrificial layer is etched according to the opening pattern to form first trenches by using the barrier layer as an etch stop layer. A medium layer material is filled in the first trenches. The sacrificial layer is etched to form second trenches by using the barrier layer as the etch stop layer. A hard mask layer material is filled in the second trenches. The medium layer material is etched to form a hard mask layer by using the barrier layer as the etch stop layer.