公开(公告)号：US20240087955A1

公开(公告)日：2024-03-14

申请号：US18241343

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Yi XU ,  Xianyuan ZHAO ,  Zhimin QI ,  Aixi ZHANG ,  Geraldine VASQUEZ ,  Dien-Yeh WU ,  Wei LEI ,  Xingyao GAO ,  Shirish PETHE ,  Wenting HOU ,  Chao DU ,  Tsung-Han YANG ,  Kyoung-Ho BU ,  Chen-Han LIN ,  Jallepally RAVI ,  Yu LEI ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876

Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

公开(公告)号：US20240047267A1

公开(公告)日：2024-02-08

申请号：US18228300

申请日：2023-07-31

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Shiyu YUE ,  Rongjun WANG

IPC: H01L21/768 ,  H01J37/32 ,  C23C14/56 ,  C23C14/58 ,  C23C16/06 ,  C23C14/06 ,  C23C16/455 ,  C23C14/18

CPC classification number: H01L21/76826 ,  H01L21/76843 ,  H01L21/76877 ,  H01J37/32091 ,  H01J37/32899 ,  C23C14/568 ,  C23C14/5846 ,  C23C16/06 ,  C23C14/0641 ,  C23C16/45525 ,  C23C14/18 ,  H01J2237/332

Abstract: Embodiments of methods and associated apparatus for filling features in a silicon-containing dielectric layer of a substrate are provided herein. In some embodiments, a method of filling features in a silicon-containing dielectric layer of a substrate includes: depositing a discontinuous liner layer in the feature via a physical vapor deposition (PVD) process in a first process chamber; performing a hydrogen plasma process in a second process chamber to form silicon-hydrogen bonds on surfaces of the feature not covered by the discontinuous liner layer; and depositing a bulk tungsten layer on the discontinuous liner layer and over the silicon-hydrogen bonds to fill the feature with tungsten in a third process chamber.

公开(公告)号：US20240363407A1

公开(公告)日：2024-10-31

申请号：US18309669

申请日：2023-04-28

Applicant: Applied Materials, Inc.

Inventor： Jie ZHANG ,  Liqi WU ,  Cory LAFOLLETT ,  Tsung-Han YANG ,  Wei WENG ,  Qihao ZHU ,  Jiang LU ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76877 ,  H01L21/02274 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76883

Abstract: Embodiments of the present disclosure generally relate to a method for forming an electrically conductive feature on a substrate. In one embodiment, the method includes forming a first conductive layer via physical vapor deposition (PVD) in an opening of a substrate. The first conductive layer has a thickness of less than 20 angstroms. The method further includes forming a second conductive layer via PVD on the first conductive layer. The first conductive layer and the second conductive layer are formed at a temperature of less than 50° C. The method further includes annealing at least a portion of the first conductive layer and the second conductive layer.

公开(公告)号：US20230343643A1

公开(公告)日：2023-10-26

申请号：US17868475

申请日：2022-07-19

Applicant: Applied Materials, Inc.

Inventor： Chih-Hsun HSU ,  Shiyu YUE ,  Wei LEI ,  Yi XU ,  Jiang LU ,  Yu LEI ,  Ziye XIONG ,  Tsung-Han YANG ,  Zhimin QI ,  Aixi ZHANG ,  Jie ZHANG ,  Liqi WU ,  Rongjun WANG ,  Shihchung CHEN ,  Meng-Shan WU ,  Chun-Chieh WANG ,  Annamalai LAKSHMANAN ,  Yixiong YANG ,  Xianmin TANG

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L21/76876 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L21/76826

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

公开(公告)号：US20240006236A1

公开(公告)日：2024-01-04

申请号：US18133065

申请日：2023-04-11

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Junyeong YUN ,  Rongjun WANG ,  Yi XU ,  Yu LEI ,  Wenting HOU ,  Xianmin TANG

IPC: H01L21/768 ,  H01J37/32

CPC classification number: H01L21/76876 ,  H01J37/321 ,  H01L21/76843 ,  H01L21/76895 ,  H01J2237/338 ,  H01J37/32899

Abstract: A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one feature. The method includes forming the nucleation layer via a cyclic vapor deposition process. The cyclic vapor deposition process includes forming a portion of the nucleation layer and then exposing the exposing the nucleation layer a chemical vapor transport (CVT) process to remove impurities from the portion of the nucleation layer. The CVT process may be performed at a temperature of 400 degrees Celsius or less and comprises forming a plasma from a processing gas comprising greater than or equal to 90% of hydrogen gas of a total flow of hydrogen gas and oxygen.

公开(公告)号：US20220415676A1

公开(公告)日：2022-12-29

申请号：US17362760

申请日：2021-06-29

Applicant: Applied Materials, Inc.

Inventor： Chaitanya Anjaneyalu PRASAD ,  Christopher Sean OLSEN ,  Lara HAWRYLCHAK ,  Erika Gabrielle HANSEN ,  Daniel C. GLOVER ,  Naman APURVA ,  Tsung-Han YANG

IPC: H01L21/67 ,  H01L21/02

Abstract: Embodiments of gas distribution modules for use with rapid thermal processing (RTP) systems and methods of use thereof are provided herein. In some embodiments, a gas distribution module for use with a RTP chamber includes: a first carrier gas line and a first liquid line fluidly coupled to a mixer, the mixer having one or more control valves configured to mix a carrier gas from the first carrier gas line and a liquid from the first liquid line in a desired ratio to form a first mixture; a vaporizer coupled to the mixer and configured to receive the first mixture in a hollow internal volume, the vaporizer having a heater configured to vaporize the first mixture; and a first gas delivery line disposed between the vaporizer and the RTP chamber to deliver the vaporized first mixture to the RTP chamber.

公开(公告)号：US20240420947A1

公开(公告)日：2024-12-19

申请号：US18210651

申请日：2023-06-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Jiajie CEN ,  Sahil Jaykumar PATEL ,  Zhimin QI ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Wei LEI ,  Yi XU ,  Yu LEI ,  Tsung-Han YANG ,  Xiaodong WANG ,  Xiangjin XIE ,  Yixiong YANG ,  Kevin KASHEFI ,  Rongjun WANG

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.

公开(公告)号：US20240014072A1

公开(公告)日：2024-01-11

申请号：US18212352

申请日：2023-06-21

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Zhimin QI ,  Yongqian GAO ,  Rongjun WANG ,  Yi XU ,  Yu LEI ,  Xingyao GAO ,  Chih-Hsun HSU ,  Xi CEN ,  Wei LEI ,  Shiyu YUE ,  Aixi ZHANG ,  Kai WU ,  Xianmin TANG

IPC: H01L21/768 ,  H01J37/32

CPC classification number: H01L21/76879 ,  H01J37/32449 ,  H01J37/32816 ,  H01J37/32422 ,  H01J2237/2001 ,  H01J37/321 ,  H01J2237/332

Abstract: A method of forming a semiconductor device structure includes forming a nucleation layer within at least one feature. The method includes exposing the nucleation layer to a nitrogen plasma treatment. The nitrogen plasma treatment preferentially treats the top field and sidewalls while leaving the bottom surface substantially untreated to encourage bottom up metal growth.

公开(公告)号：US20230420295A1

公开(公告)日：2023-12-28

申请号：US18133102

申请日：2023-04-11

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Xingyao GAO ,  Shiyu YUE ,  Chih-Hsun HSU ,  Shirish PETHE ,  Rongjun WANG ,  Yi XU ,  Wei LEI ,  Yu LEI ,  Aixi ZHANG ,  Xianyuan ZHAO ,  Zhimin QI ,  Jiang LU ,  Xianmin TANG

IPC: H01L21/768 ,  H01L21/285 ,  H01J37/32

CPC classification number: H01L21/76877 ,  H01L21/76876 ,  H01L21/76865 ,  H01L21/2855 ,  H01J2237/338 ,  H01L21/76856 ,  H01L21/76861 ,  H01J37/32899 ,  H01L21/76843

Abstract: A method and apparatus for tungsten gap-fill in semiconductor devices are provided. The method includes performing a gradient oxidation process to oxidize exposed portions of a liner layer, wherein the gradient oxidation process preferentially oxidizes an overhang portion of the liner layer, which obstructs or blocks top openings of one or more features formed within a field region of a substrate. The method further includes performing an etchback process to remove or reduce the oxidized overhang portion of the liner layer, exposing the liner layer to a chemical vapor transport (CVT) process to remove metal oxide remaining from the gradient oxidation process and the etchback process, and performing a tungsten gap-fill process to fill or partially fill the one or more features.

公开(公告)号：US20230207291A1

公开(公告)日：2023-06-29

申请号：US17716419

申请日：2022-04-08

Applicant: Applied Materials, Inc.

Inventor： Christopher S. OLSEN ,  Rene GEORGE ,  Tsung-Han YANG ,  David KNAPP ,  Lara HAWRYLCHAK

IPC: H01J37/32 ,  H01L21/02 ,  C23C8/36 ,  C23C8/12

CPC classification number: H01J37/32816 ,  H01L21/02238 ,  H01L21/0223 ,  H01L21/02252 ,  H01J37/3244 ,  H01J37/32357 ,  H01J37/321 ,  C23C8/36 ,  C23C8/12 ,  H01L27/115

Abstract: A method and apparatus for growing an oxide layer within a feature of a substrate is described herein. The method is suitable for use in semiconductor manufacturing. The oxide layer is formed by exposing a substrate to both a high pressure oxidant exposure and a lower pressure oxygen containing plasma exposure. The high pressure oxidant exposure is performed at a pressure of greater than 10 Torr, while the lower pressure oxygen containing plasma exposure is performed at a pressure of less than about 10 Torr. The features are high-aspect ratio trenches or holes within a stack of silicon oxide and silicon nitride layers.