公开(公告)号：US20240194527A1

公开(公告)日：2024-06-13

申请号：US18197846

申请日：2023-05-16

Applicant: Applied Materials, Inc.

Inventor： Sahil Jaykumar PATEL ,  Xianyuan ZHAO ,  Wei LEI ,  Aixi ZHANG ,  Yi XU ,  Yu LEI

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/53266

Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes depositing an amorphous interlayer atop a first layer on a substrate, wherein the first layer is a metal-containing layer, and depositing a metal layer atop the amorphous interlayer.

公开(公告)号：US20240371771A1

公开(公告)日：2024-11-07

申请号：US18423437

申请日：2024-01-26

Applicant: Applied Materials, Inc.

Inventor： Sahil Jaykumar PATEL ,  Wei LEI ,  Tuerxun AILIHUMAER ,  Joung Joo LEE ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L23/532 ,  H01L21/768

Abstract: Embodiments of the disclosure include an apparatus and method of forming a semiconductor structure that includes metal contacts with a low resistance. In some embodiments, the semiconductor device generally includes an interconnect. The interconnect generally includes a dielectric layer with a tungsten (W) plug formed therein, a feature formed in the dielectric layer and over the W plug, a liner layer formed on an exposed surface of the W plug and on sidewalls of the feature, an interruption layer formed on the liner layer, and a conductive material substantially filling the feature. The liner layer includes molybdenum (Mo) or W, and the interruption layer includes Mo.

公开(公告)号：US20250006518A1

公开(公告)日：2025-01-02

申请号：US18753006

申请日：2024-06-25

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Wei LEI ,  Yu LEI ,  Ju Hyun OH ,  Zhimin QI ,  Sahil Jaykumar PATEL ,  Yi XU ,  Aixi ZHANG ,  Bingqian LIU ,  Cong TRINH ,  Xianmin TANG ,  Hayrensa ABLAT

IPC: H01L21/67 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments herein relate to a method, semiconductor device structures, and multi-chamber processing system for exposing a semiconductor device structure to an oxidizing plasma to form an oxide layer on at least one electrical connection formed in at least one feature formed within a dielectric layer of the semiconductor device structure, performing an etch process to remove the oxide layer and form an etch recess between a portion of the electrical connection and the dielectric layer At least a portion of the etch recess extends underneath at least a portion of the dielectric layer, and filling the at least one feature and the etch recess with a metal material.

公开(公告)号：US20250079199A1

公开(公告)日：2025-03-06

申请号：US18458146

申请日：2023-08-29

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Sahil Jaykumar PATEL ,  Yu LEI ,  Wei LEI ,  Chih-Hsun HSU ,  Yi XU ,  Abulaiti HAIRISHA ,  Cong TRINH ,  Yixiong YANG ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Rongjun WANG

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/3213

Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

公开(公告)号：US20240420947A1

公开(公告)日：2024-12-19

申请号：US18210651

申请日：2023-06-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Jiajie CEN ,  Sahil Jaykumar PATEL ,  Zhimin QI ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Wei LEI ,  Yi XU ,  Yu LEI ,  Tsung-Han YANG ,  Xiaodong WANG ,  Xiangjin XIE ,  Yixiong YANG ,  Kevin KASHEFI ,  Rongjun WANG

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.