公开(公告)号：US20240194605A1

公开(公告)日：2024-06-13

申请号：US18534333

申请日：2023-12-08

Applicant: Applied Materials, Inc.

Inventor： Mohammad Mahdi TAVAKOLI ,  Avgerinos V. GELATOS ,  Jiajie CEN ,  Kevin KASHEFI ,  Joung Joo LEE ,  Zhihui LIU ,  Yang ZHOU ,  Zhiyuan WU ,  Meng-Shan WU

IPC: H01L23/532 ,  H01J37/32 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01J37/32357 ,  H01L21/02068 ,  H01L21/76843 ,  H01L21/76877 ,  H01J2237/335

Abstract: A semiconductor structure includes a first level comprising a metal layer within a first dielectric layer formed on a substrate, a second level formed on the first level, the second level comprising an interconnect within a second dielectric layer and a barrier layer formed around the interconnect, and a metal capping layer disposed at an interface between the metal layer and the interconnect, wherein the metal capping layer comprises tungsten (W) and has a thickness of between 20 Å and 40 Å.

公开(公告)号：US20240290655A1

公开(公告)日：2024-08-29

申请号：US18115561

申请日：2023-02-28

Applicant: Applied Materials, Inc.

Inventor： Zheng JU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng Q. LIU ,  Feng CHEN

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5226 ,  H01L21/76862 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method of selectively filling a via with a simultaneous liner deposition in a semiconductor structure includes forming a passivation layer selectively on an exposed surface of a conductive layer within a via formed in a dielectric layer formed over the conductive layer, forming a barrier layer selectively on inner sidewalls of the via and a trench formed in the dielectric layer, selectively filling the via with a first conductive material at least partially and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench, to form a liner on the inner sidewalls of the via and the trench, and filling the remaining of the via and the trench with a second conductive material.

公开(公告)号：US20230098561A1

公开(公告)日：2023-03-30

申请号：US17489089

申请日：2021-09-29

Applicant: Applied Materials, Inc.

Inventor： Jiajie CEN ,  Da HE ,  Yi XU ,  Yu LEI

IPC: H01L21/768 ,  H01L21/02

Abstract: A method of gap filling a feature on a substrate decreases the feature-to-feature gap fill height variation by using a tungsten halide soak treatment. In some embodiments, the method may include heating a substrate to a temperature of approximately 350 degrees Celsius to approximately 450 degrees Celsius, exposing the substrate to a tungsten halide gas at a process pressure of approximately 5 Torr to approximately 25 Torr, soaking the substrate for a soak time of approximately 5 seconds to approximately 60 seconds with the tungsten halide gas, and performing a metal preclean process and a gap fill deposition on a plurality of features on the substrate after soaking of the substrate has completed.

公开(公告)号：US20240153816A1

公开(公告)日：2024-05-09

申请号：US17980850

申请日：2022-11-04

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng CHEN

IPC: H01L21/768

CPC classification number: H01L21/76855 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76882

Abstract: A method for forming a metal liner layer for an interconnect uses a multi-metal deposition process to produce a reduced thickness liner. The back-end-of-the-line packaging process may include forming a metal liner layer by depositing a ruthenium layer with a first thickness of approximately 5 angstroms or less and depositing a first cobalt layer with a second thickness of approximately 20 angstroms or less. In some embodiments, the ruthenium layer may be deposited on a previously formed barrier layer and then undergoes a treatment process before depositing the first cobalt layer. In some embodiments, the first cobalt layer may be deposited on the ruthenium layer or the ruthenium layer maybe deposited on the first cobalt layer. In some embodiments, the ruthenium layer is deposited on the first cobalt layer and a second cobalt layer is deposited on the ruthenium layer.

公开(公告)号：US20240038541A1

公开(公告)日：2024-02-01

申请号：US17961153

申请日：2022-10-06

Applicant: Applied Materials, Inc.

Inventor： Jiajie CEN ,  Xiaodong WANG ,  Kevin KASHEFI ,  Shi YOU

IPC: H01L21/3065

CPC classification number: H01L21/3065

Abstract: Methods for cleaning oxides from a substrate surface are performed without affecting low-k dielectric or carbon materials on the substrate. In some embodiments, the method may include performing a preclean process with a chlorine-based soak to remove oxides from a surface of a substrate in a back end of the line (BEOL) process and treating the surface of the substrate with a remote plasma with a hydrogen gas and at least one inert gas to remove residual chlorine residue from the surface of the substrate without damaging low-k dielectric material or carbon material on the substrate.

公开(公告)号：US20250062160A1

公开(公告)日：2025-02-20

申请号：US18749589

申请日：2024-06-20

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng CHEN ,  Kevin KASHEFI ,  Chengyu LIU

IPC: H01L21/768 ,  H01L21/02

Abstract: A method of forming a metal interconnect in a semiconductor structure includes performing a barrier layer deposition process to deposit a barrier layer within an opening formed through a dielectric layer, performing a liner deposition process to deposit a liner layer on the barrier layer, performing a metal treatment process to implant metal dopants into a surface of the liner layer, and performing a gap fill process to form a metal interconnect on the metal treated surface of the liner layer within the opening.

公开(公告)号：US20240404803A1

公开(公告)日：2024-12-05

申请号：US18647819

申请日：2024-04-26

Applicant: Applied Materials, Inc.

Inventor： Yoon Ah SHIN ,  Jiajie CEN ,  Zhiyuan WU ,  Bencherki MEBARKI ,  Kevin KASHEFI ,  Joung Joo LEE ,  Xianmin TANG

IPC: H01J37/32

Abstract: Embodiments of the present disclosure generally relate to a low temperature non-plasma containing preclean process to selectively remove contaminants from the surface of a substrate, such as halogen containing and/or metal oxide containing contaminants. The non-plasma containing precleaning process is performed at a low temperature by use of a microwave source that is configured to provide microwave energy to the processing gases disposed within a processing chamber. The non-plasma low temperature preclean process is effective in reducing halogen containing residues, such as fluorine and chlorine containing residues formed on a surface of a substrate.

公开(公告)号：US20250157856A1

公开(公告)日：2025-05-15

申请号：US18912536

申请日：2024-10-10

Applicant: Applied Materials, Inc.

Inventor： Jiajie CEN ,  Zheng JU ,  Feng Q. LIU ,  Ying-Bing JIANG ,  Shiyu YUE ,  Xianmin TANG

IPC: H01L21/768 ,  C23C16/14 ,  C23C16/50

Abstract: Embodiments of the invention provide a method of forming a molybdenum (Mo) capping layer that is used to prevent copper diffusion in interconnect boundary regions of a formed semiconductor device. The molybdenum capping will improve copper boundary region properties to promote adhesion, decrease diffusion and copper agglomeration. Embodiments provide that a molybdenum capping layer may be selectively deposited on a surface of a copper interconnect structures formed in a dielectric layer formed on a substrate.

公开(公告)号：US20240420947A1

公开(公告)日：2024-12-19

申请号：US18210651

申请日：2023-06-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Jiajie CEN ,  Sahil Jaykumar PATEL ,  Zhimin QI ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Wei LEI ,  Yi XU ,  Yu LEI ,  Tsung-Han YANG ,  Xiaodong WANG ,  Xiangjin XIE ,  Yixiong YANG ,  Kevin KASHEFI ,  Rongjun WANG

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.

公开(公告)号：US20240186181A1

公开(公告)日：2024-06-06

申请号：US18074335

申请日：2022-12-02

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Qihao ZHU ,  Zheng JU ,  Yang ZHOU ,  Jiajie CEN ,  Feng Q. LIU ,  Zhiyuan WU ,  Feng CHEN ,  Kevin KASHEFI ,  Xianmin TANG ,  Jeffrey W. ANTHIS ,  Mark Joseph SALY

IPC: H01L21/768 ,  H01L21/3205

CPC classification number: H01L21/76849 ,  H01L21/32051 ,  H01L21/76877

Abstract: Methods to deposit a metal cap for an interconnect are disclosed. In embodiments, a method comprises contacting the substrate with an alkyl halide and a ruthenium metal precursor to form a metal cap for an interconnect.