公开(公告)号：US20240128075A1

公开(公告)日：2024-04-18

申请号：US18378234

申请日：2023-10-10

Applicant: Applied Materials, Inc.

Inventor： Peijiao FANG ,  Mingdong LI ,  Chengyu LIU

IPC: H01L21/02 ,  C23C16/52

CPC classification number: H01L21/02164 ,  C23C16/52 ,  H01L21/0228 ,  H01L21/0262

Abstract: Methods for depositing amorphous silicon films via physical vapor deposition processes are disclosed. In some embodiments, a method of depositing amorphous silicon in a physical vapor deposition (PVD) process chamber includes (a) depositing an amorphous silicon layer atop a surface of a substrate disposed on a substrate support via a physical vapor deposition process, in the meanwhile amorphous silicon is also deposited atop components within the PVD process chamber; and depositing a glue layer atop the amorphous silicon deposited on the components. The glue layer can be a silicon compound. The silicon compound can be a compound of silicon with one or more of carbon, nitrogen, or oxygen. In some embodiments, the silicon compound is SiC, SiN, SiO, SiCN, or SiON.

公开(公告)号：US20250062160A1

公开(公告)日：2025-02-20

申请号：US18749589

申请日：2024-06-20

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng CHEN ,  Kevin KASHEFI ,  Chengyu LIU

IPC: H01L21/768 ,  H01L21/02

Abstract: A method of forming a metal interconnect in a semiconductor structure includes performing a barrier layer deposition process to deposit a barrier layer within an opening formed through a dielectric layer, performing a liner deposition process to deposit a liner layer on the barrier layer, performing a metal treatment process to implant metal dopants into a surface of the liner layer, and performing a gap fill process to form a metal interconnect on the metal treated surface of the liner layer within the opening.

公开(公告)号：US20240271266A1

公开(公告)日：2024-08-15

申请号：US18108325

申请日：2023-02-10

Applicant: Applied Materials, Inc.

Inventor： Chengyu LIU ,  Xianmin TANG

IPC: C23C14/00 ,  C23C14/10 ,  C23C14/34 ,  H01J37/317

CPC classification number: C23C14/0036 ,  C23C14/10 ,  C23C14/345 ,  C23C14/3485 ,  C23C14/3492 ,  H01J37/3178 ,  H01J2237/2001

Abstract: Methods for forming an airgap within a structure of a substrate, comprising anisotropically depositing a layer of SiO2 on a top surface of the substrate to form a cap over the structure and the airgap disposed between the cap and a bottom surface of the structure via reactive negative ion sputtering of a silicon (Si) target in a presence of diatomic oxygen in an inert carrier gas, wherein the target is pulsed at a voltage of less than or equal to about −200 V at a pulse rate of greater than about 10 KHz. A substrate having an airgap is also disclosed.

公开(公告)号：US20230113965A1

公开(公告)日：2023-04-13

申请号：US17499955

申请日：2021-10-13

Applicant: Applied Materials, Inc.

Inventor： Chengyu LIU ,  Ruitong XIONG ,  Bo XIE ,  Xianmin TANG ,  Yijun LIU ,  Li-Qun XIA

IPC: H01L21/02 ,  H01L21/3205

Abstract: A method for dielectric filling of a feature on a substrate yields a seamless dielectric fill with high-k for narrow features. In some embodiments, the method may include depositing a metal material into the feature to fill the feature from a bottom of the feature wherein the feature has an opening ranging from less than 20 nm to approximately 150 nm at an upper surface of the substrate and wherein depositing the metal material is performed using a high ionization physical vapor deposition (PVD) process to form a seamless metal gap fill and treating the seamless metal gap fill by oxidizing/nitridizing the metal material of the seamless metal gap fill with an oxidation/nitridation process to form dielectric material wherein the seamless metal gap fill is converted into a seamless dielectric gap fill with high-k dielectric material.

公开(公告)号：US20220301828A1

公开(公告)日：2022-09-22

申请号：US17203786

申请日：2021-03-17

Applicant: Applied Materials, Inc.

Inventor： Wei DOU ,  Yong CAO ,  Mingdong LI ,  Shane LAVAN ,  Jothilingam RAMALINGAM ,  Chengyu LIU

IPC: H01J37/32 ,  C23C14/14 ,  C23C14/06 ,  C23C14/34 ,  C23C14/54

Abstract: Embodiments of methods and apparatus for reducing particle formation in physical vapor deposition (PVD) chambers are provided herein. In some embodiments, a method of reducing particle formation in a PVD chamber includes: performing a plurality of first deposition processes on a corresponding series of substrates disposed on a substrate support in the PVD chamber, wherein the PVD chamber includes a cover ring disposed about the substrate support and having a texturized outer surface, and wherein a silicon nitride (SiN) layer having a first thickness is deposited onto the texturized outer surface during each of the plurality of first deposition processes; and performing a second deposition process on the cover ring between subsets of the plurality of first deposition processes to deposit an amorphous silicon layer having a second thickness onto an underlying silicon nitride (SiN) layer.