公开(公告)号：US20250112091A1

公开(公告)日：2025-04-03

申请号：US18899407

申请日：2024-09-27

Applicant: Applied Materials, Inc.

Inventor： Jianqiu GUO ,  Dong WANG ,  Liqi WU ,  Yiyang WAN ,  Shumao ZHANG ,  Qihao ZHU ,  Weifeng YE ,  Jiang LU ,  Shihchung CHEN

IPC: H01L21/768 ,  C23C16/02 ,  C23C16/42 ,  C23C16/455 ,  H01J37/32 ,  H01L21/285 ,  H01L23/532

Abstract: A contact structure includes a cavity comprising a device contact formed on a surface of a substrate, a bottom surface, and sidewalls. A metal silicide layer disposed over the surface of the device contact, the bottom surface, and the sidewalls of the cavity, and a treated surface formed over a portion of the metal silicide layer disposed over the sidewalls of the cavity.

公开(公告)号：US20250054767A1

公开(公告)日：2025-02-13

申请号：US18646055

申请日：2024-04-25

Applicant: Applied Materials, Inc.

Inventor： Qihao ZHU ,  Shumao ZHANG ,  Weifeng YE ,  Yiyang WAN ,  Gary HOW ,  Jianqiu GUO ,  Dong WANG ,  Shihchung CHEN ,  Liqi WU ,  Jiang LU

IPC: H01L21/285 ,  C23C16/02 ,  C23C16/04 ,  C23C16/14 ,  C23C16/42 ,  C23C16/455 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32 ,  H01L21/02 ,  H01L21/768

Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.

公开(公告)号：US20250054812A1

公开(公告)日：2025-02-13

申请号：US18400819

申请日：2023-12-29

Applicant: Applied Materials, Inc.

Inventor： Qihao ZHU ,  Shumao ZHANG ,  Weifeng YE ,  Yiyang WAN ,  Gary HOW ,  Jianqiu GUO ,  Dong WANG ,  Shihchung CHEN ,  Liqi WU ,  Jiang LU

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.

公开(公告)号：US20230343643A1

公开(公告)日：2023-10-26

申请号：US17868475

申请日：2022-07-19

Applicant: Applied Materials, Inc.

Inventor： Chih-Hsun HSU ,  Shiyu YUE ,  Wei LEI ,  Yi XU ,  Jiang LU ,  Yu LEI ,  Ziye XIONG ,  Tsung-Han YANG ,  Zhimin QI ,  Aixi ZHANG ,  Jie ZHANG ,  Liqi WU ,  Rongjun WANG ,  Shihchung CHEN ,  Meng-Shan WU ,  Chun-Chieh WANG ,  Annamalai LAKSHMANAN ,  Yixiong YANG ,  Xianmin TANG

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L21/76876 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L21/76826

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

公开(公告)号：US20220064785A1

公开(公告)日：2022-03-03

申请号：US17010518

申请日：2020-09-02

Applicant: Applied Materials, Inc.

Inventor： Muhannad MUSTAFA ,  Haoyan SHA ,  Muhammad M. RASHEED ,  Chi-Chou LIN ,  Mario D. SILVETTI ,  Bin CAO ,  Shihchung CHEN ,  Yongjing LIN

IPC: C23C16/44

Abstract: Embodiments of the present disclosure generally relate chamber lids and methods of using such for gas-phase particle reduction. In an embodiment is provided a chamber lid that includes a top wall, a bottom wall, a plurality of vertical sidewalls, and an interior volume within the chamber lid defined by the top wall, the bottom wall, and the plurality of vertical sidewalls. The chamber lid further includes a plurality of air flow apertures, wherein the plurality of air flow apertures is configured to fluidly communicate air into the interior volume and out of the interior volume, and a mesh disposed on a face of at least one of the air flow apertures of the plurality of air flow apertures. In another embodiment is provided a method of processing a substrate in a substrate processing chamber, the substrate processing chamber comprising a chamber lid as described herein.