METHODS FOR FORMING LOW RESISTIVITY CONTACTS

    公开(公告)号:US20240379363A1

    公开(公告)日:2024-11-14

    申请号:US18582977

    申请日:2024-02-21

    Abstract: Methods are provided. In some embodiments, a method of forming a contact structure on a semiconductor substrate includes disposing a selective metal silicide layer on a surface of a contact structure by maintaining a first temperature of a substrate and providing a first carrier gas, a first metal-containing precursor, and a first hydrogen-containing precursor to a first deposition chamber. The method includes disposing a partially selective metal layer on a surface of the selective metal silicide layer and one or more surfaces of a cavity by maintaining a second temperature of the substrate and providing a second carrier gas, a second metal-containing precursor, and a reducing agent to the first deposition chamber or a second deposition chamber. The second metal-containing precursor and the reducing agent are introduced to the first deposition chamber or the second deposition chamber at a chamber pressure of about 50 T to about 150 T.

    METHOD FOR FORMING A LAYER
    2.
    发明申请

    公开(公告)号:US20200161181A1

    公开(公告)日:2020-05-21

    申请号:US16669082

    申请日:2019-10-30

    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.

    SELECTIVE CAPPING FOR GATE-ALL-AROUND FIELD EFFECT TRANSISTORS

    公开(公告)号:US20250079239A1

    公开(公告)日:2025-03-06

    申请号:US18459524

    申请日:2023-09-01

    Abstract: Embodiments of the disclosure include a method of forming a gate-all-around (GAA) contact structure on a semiconductor substrate. The method will include removing material from surfaces of a feature formed in a surface of a substrate that includes a plurality of features that each include a plurality of source/drain contact surfaces, selectively forming a reaction product material over a surface of each of the plurality of source/drain contact surfaces, heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts, selectively forming a first metal layer on the surface of each of the plurality of contacts, selectively forming a second metal layer on the first metal layer, and filling the feature with a conductor material, wherein the conductor material comprises tungsten (W) or molybdenum (Mo).

    METHOD OF FORMING A MEOL CONTACT STRUCTURE

    公开(公告)号:US20240379768A1

    公开(公告)日:2024-11-14

    申请号:US18196833

    申请日:2023-05-12

    Abstract: Embodiments of the disclosure include a method of forming contact structure on a semiconductor substrate. The method includes treating a native oxide layer formed on a contact junction, wherein treating the native oxide layer forms a silica salt layer on the contact junction disposed within a contact feature that includes one or more surfaces that comprise silicon nitride. Then exposing the silica salt layer and the one or more surfaces to a plasma comprising oxygen, wherein the plasma forms a silicon oxynitride material on the one or more surfaces. Then removing the second silica salt layer, selectively forming a metal silicide layer on the contact junction, and then filling the contact feature with a metal, wherein filling the feature comprises selectively depositing a metal layer over the selectively formed metal silicide layer.

    METHODS OF FORMING VOID AND SEAM FREE METAL FEATURES

    公开(公告)号:US20220359279A1

    公开(公告)日:2022-11-10

    申请号:US17316649

    申请日:2021-05-10

    Abstract: Embodiments herein are generally directed to methods of forming high aspect ratio metal contacts and/or interconnect features, e.g., tungsten features, in a semiconductor device. Often, conformal deposition of tungsten in a high aspect ratio opening results in a seam and/or void where the outward growth of tungsten from one or more walls of the opening meet. Thus, the methods set forth herein provide for a desirable bottom up tungsten bulk fill to avoid the formation of seams and/or voids in the resulting interconnect features, and provide an improved contact metal structure and method of forming the same. In some embodiments, an improved overburden layer or overburden layer structure is formed over the field region of the substrate to enable the formation of a contact or interconnect structure that has improved characteristics over conventionally formed contacts or interconnect structures.

Patent Agency Ranking