公开(公告)号：US20240096993A1

公开(公告)日：2024-03-21

申请号：US18151481

申请日：2023-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shen-Yang Lee ,  Hsiang-Pi Chang ,  Huang-Lin Chao

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/78696

摘要： A method for tuning a threshold voltage of a transistor is disclosed. A channel layer is formed over a substrate. An interfacial layer is formed over and surrounds the channel layer. A gate dielectric layer is formed over and surrounds the interfacial layer. A dipole layer is formed over and wraps around the gate dielectric layer by performing a cyclic deposition etch process, and the dipole layer includes dipole metal elements and has a substantially uniform thickness. A thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface, and then the dipole layer is removed.

公开(公告)号：US20240055501A1

公开(公告)日：2024-02-15

申请号：US17887487

申请日：2022-08-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pinyen Lin ,  Chung-Liang Cheng ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Huang-Lin Chao

IPC分类号： H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L29/45 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/28518 ,  H01L29/66742 ,  H01L29/66439

摘要： A semiconductor device and the manufacturing method thereof are described. The device includes semiconductor channel sheets, source and drain regions and a gate structure. The semiconductor channel sheets are arranged in parallel and spaced apart from one another. The source and drain regions are disposed beside the semiconductor channel sheets. The gate structure is disposed around and surrounding the semiconductor channel sheets. The silicide layer is disposed on the source region or the drain region. A contact structure is disposed on the silicide layer on the source region or the drain region. The contact structure includes a metal contact and a liner, and the silicide layer is in contact with the metal contact, and the liner is separate from the silicide layer by the metal contact.

公开(公告)号：US11688644B2

公开(公告)日：2023-06-27

申请号：US17245768

申请日：2021-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chu-An Lee ,  Chen-Hao Wu ,  Peng-Chung Jangjian ,  Chun-Wen Hsiao ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC分类号： H01L21/8234 ,  H01L21/76 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/3105

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L21/31053

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. A first gate structure and a second gate structure are across the first and second fins, respectively. An insulating structure is formed between the first gate structure and the second gate structure and includes a first insulating layer separating the first fin from the second fin, a capping structure formed in the first insulating layer, and a second insulating layer covered by the first insulating layer and the capping structure.

公开(公告)号：US20220195246A1

公开(公告)日：2022-06-23

申请号：US17688869

申请日：2022-03-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Hung Liao ,  An-Hsuan Lee ,  Shen-Nan Lee ,  Teng-Chun Tsai ,  Chen-Hao Wu ,  Huang-Lin Chao

IPC分类号： C09G1/02 ,  H01L21/8238 ,  H01L21/321 ,  H01L21/306 ,  C09K3/14 ,  C09G1/06 ,  C09G1/00 ,  C09K13/06 ,  C09G1/04 ,  B24B1/00 ,  B24B37/04

摘要： A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.

公开(公告)号：US20240297244A1

公开(公告)日：2024-09-05

申请号：US18177381

申请日：2023-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Ming Chang ,  Yao-Sheng Huang ,  Hsiang-Pi Chang ,  Yi-Ruei Jhan ,  Huang-Lin Chao

IPC分类号： H01L29/775 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545

摘要： A method for fabricating semiconductor devices includes forming a stack structure protruding from a substrate and including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked on top of one another. The method includes forming an isolation structure overlaying the substrate and a lower portion of the stack structure. The method includes implanting dopants into at least an upper portion of the isolation structure.

公开(公告)号：US12040364B2

公开(公告)日：2024-07-16

申请号：US18297868

申请日：2023-04-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsueh-Wen Tsau ,  Chun-I Wu ,  Ziwei Fang ,  Huang-Lin Chao ,  I-Ming Chang ,  Chung-Liang Cheng ,  Chih-Cheng Lin

IPC分类号： H01L29/40 ,  H01L21/28 ,  H01L21/768 ,  H01L23/532 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/522 ,  H01L29/06

CPC分类号： H01L29/401 ,  H01L21/28247 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28088 ,  H01L21/28568 ,  H01L23/5226 ,  H01L29/0673

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.

公开(公告)号：US20240178319A1

公开(公告)日：2024-05-30

申请号：US18431921

申请日：2024-02-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiang-Pi Chang ,  Yen-Tien Tung ,  Dawei Heh ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Tzer-Min Shen ,  Huang-Lin Chao

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/78391 ,  H01L29/401 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/6684

摘要： A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.

公开(公告)号：US11842927B2

公开(公告)日：2023-12-12

申请号：US17330272

申请日：2021-05-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： I-Ming Chang ,  Chung-Liang Cheng ,  Hsiang-Pi Chang ,  Hung-Chang Sun ,  Yao-Sheng Huang ,  Yu-Wei Lu ,  Fang-Wei Lee ,  Ziwei Fang ,  Huang-Lin Chao

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L29/423 ,  H01L21/8238

CPC分类号： H01L21/823431 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/76832 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.

公开(公告)号：US20230386938A1

公开(公告)日：2023-11-30

申请号：US18447239

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huiching Chang ,  I-Ming Chang ,  Huang-Lin Chao

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092

CPC分类号： H01L21/823857 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/7851 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02192 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66742 ,  H01L27/0924

摘要： A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.

公开(公告)号：US20220278002A1

公开(公告)日：2022-09-01

申请号：US17187283

申请日：2021-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yao-Sheng Huang ,  I-MING CHANG ,  Huang-Lin Chao

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.