公开(公告)号：US10714411B2

公开(公告)日：2020-07-14

申请号：US15921852

申请日：2018-03-15

申请人： GLOBALFOUNDRIES INC.

发明人： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

IPC分类号： H01L23/48 ,  H01L23/488 ,  H01L25/065

摘要： An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

公开(公告)号：US20190067210A1

公开(公告)日：2019-02-28

申请号：US15690398

申请日：2017-08-30

申请人： GLOBALFOUNDRIES INC.

发明人： Nicholas A. Polomoff ,  Vincent J. McGahay

IPC分类号： H01L23/00 ,  H01L23/58

摘要： A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.

公开(公告)号：US10153232B2

公开(公告)日：2018-12-11

申请号：US15498083

申请日：2017-04-26

申请人： GLOBALFOUNDRIES Inc.

发明人： Robert J. Fox, III ,  Kevin M. Boyd ,  Nicholas A. Polomoff ,  Roderick A. Augur ,  Jeannine M. Trewhella

IPC分类号： H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

摘要： A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

公开(公告)号：US10068859B1

公开(公告)日：2018-09-04

申请号：US15662334

申请日：2017-07-28

申请人： GLOBALFOUNDRIES INC.

发明人： Nicholas A. Polomoff ,  Mohamed Rabie ,  Victoria L. Calero Diaz Del Castillo ,  Danielle Degraw ,  Michael Hecker

IPC分类号： H01L23/58 ,  H01L23/00 ,  H01L23/544

摘要： A structure for arresting the propagation of cracks during the dicing of a semiconductor wafer into individual chips includes a monolithic metallic plate that traverses multiple dielectric layers peripheral to an active region of a chip. One or more metallic plates may be formed using lithography and electroplating techniques between the active device region and a peripheral kerf region, where each metallic plate includes a concave feature that faces the kerf region of the wafer.

公开(公告)号：US20200066656A1

公开(公告)日：2020-02-27

申请号：US16109867

申请日：2018-08-23

申请人： GLOBALFOUNDRIES INC.

发明人： Nicholas A. Polomoff ,  Andreas D. Stricker ,  Anupam I. Arora

IPC分类号： H01L23/58 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  G02B6/12

摘要： Embodiments of the disclosure provide a photonic integrated circuit (PIC) die including: a semiconductor substrate; active circuitry on the semiconductor substrate; an inter-level dielectric (ILD) over the semiconductor substrate and the active circuitry; a photonic element extending from the active circuitry on the semiconductor substrate; and a guard ring on the semiconductor substrate and within the ILD, the guard ring surrounding the active circuitry, the guard ring including: a conductive body, and a conductive bridge element extending over the photonic element.

公开(公告)号：US10546822B2

公开(公告)日：2020-01-28

申请号：US15690398

申请日：2017-08-30

申请人： GLOBALFOUNDRIES INC.

发明人： Nicholas A. Polomoff ,  Vincent J. McGahay

IPC分类号： H01L21/70 ,  H01L23/58 ,  H01L21/768 ,  H01L23/00

摘要： A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.

公开(公告)号：US20190287879A1

公开(公告)日：2019-09-19

申请号：US15921852

申请日：2018-03-15

申请人： GLOBALFOUNDRIES INC.

发明人： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

IPC分类号： H01L23/488 ,  H01L25/065

摘要： An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

公开(公告)号：US10090258B1

公开(公告)日：2018-10-02

申请号：US15713843

申请日：2017-09-25

申请人： GLOBALFOUNDRIES Inc.

发明人： Kevin Boyd ,  Robert Fox ,  Jeannine Trewhella ,  Roderick Alan Augur ,  Nicholas A. Polomoff

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L23/535

摘要： One illustrative crack-stop structure disclosed herein may include a first crack-stop metallization layer comprising a first metal line layer that has a plurality of openings formed therein and a second crack-stop metallization layer positioned above and adjacent the first crack-stop metallization layer, wherein the second crack-stop metallization layer has a second metal line layer and a via layer, and wherein the via layer comprises a plurality of vias having a portion that extends at least partially into the openings in the first metal line layer of the first crack-stop metallization layer so as to thereby form a stepped, non-planar interface between the first metal line layer of the first crack-stop metallization layer and the via layer of the second crack-stop metallization layer.

公开(公告)号：US10109600B1

公开(公告)日：2018-10-23

申请号：US15702316

申请日：2017-09-12

申请人： GLOBALFOUNDRIES INC.

发明人： Vincent J. McGahay ,  Nicholas A. Polomoff

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

摘要： The present disclosure relates to semiconductor structures and, more particularly, to continuous crackstop structures and methods of manufacture. The structure includes a continuous crackstop having a wall which switches back (switchbacks) on itself multiple times to form an enclosure about an active area of a chip.

公开(公告)号：US10770412B2

公开(公告)日：2020-09-08

申请号：US16109867

申请日：2018-08-23

申请人： GLOBALFOUNDRIES INC.

发明人： Nicholas A. Polomoff ,  Andreas D. Stricker ,  Anupam I Arora

IPC分类号： H01L23/58 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  G02B6/12

摘要： Embodiments of the disclosure provide a photonic integrated circuit (PIC) die including: a semiconductor substrate; active circuitry on the semiconductor substrate; an inter-level dielectric (ILD) over the semiconductor substrate and the active circuitry; a photonic element extending from the active circuitry on the semiconductor substrate; and a guard ring on the semiconductor substrate and within the ILD, the guard ring surrounding the active circuitry, the guard ring including: a conductive body, and a conductive bridge element extending over the photonic element.