公开(公告)号：US20240170351A1

公开(公告)日：2024-05-23

申请号：US17992010

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/167 ,  H01L23/49833 ,  H01L23/5385 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15788

Abstract: Architectures and processes for redistribution layers in a dielectric cavity to enable an embedded component in semiconductor packaging. The architectures pattern redistribution layers (RDL) over a thick seed and remove dielectric material from the RDL conductive contacts to create the dielectric cavity. The architectures enable 2-sided connections for embedded components in the dielectric cavity with minimal disruption to existing process infrastructure. Such an approach can be used not only for integration of photonic devices, but also for any semiconductor packaging requiring dual sided connection within a dielectric cavity.

公开(公告)号：US11929316B2

公开(公告)日：2024-03-12

申请号：US18111100

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Eungkyu Kim ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/13016 ,  H01L2224/13541 ,  H01L2224/1355 ,  H01L2224/16013 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17055 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81345 ,  H01L2224/81815

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US20240079358A1

公开(公告)日：2024-03-07

申请号：US17939880

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Siva Sai Kishore Palli ,  Venkata Rama Satya Pradeep Vempaty ,  Wen How Sim ,  Chen Yu Huang ,  Harjashan Veer Singh

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05573 ,  H01L2224/16014 ,  H01L2224/1607 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/384

Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate and a die stack carried by the package substrate. The die stack can include at least a first semiconductor die carried by the package substrate, a second semiconductor die carried by the first semiconductor die. The first semiconductor die can have an upper surface and a first bond pad carried by the upper surface that includes a curvilinear concave depression formed in an uppermost surface of the first bond pad. The second semiconductor die has a lower surface and a second bond pad carried by the lower surface. The die stack can also include solder structure electrically coupling the first and second bond pads and at least partially filling the curvilinear concave depression formed in the uppermost surface of the first bond pad.

公开(公告)号：US20230354523A1

公开(公告)日：2023-11-02

申请号：US18220026

申请日：2023-07-10

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Akito Yoshida ,  Mahmoud Dreiza ,  Curtis Michael Zwenger

IPC: H05K1/14 ,  H01L23/31 ,  H01L23/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H01L21/56 ,  H01L23/498 ,  H05K3/36 ,  H05K3/40

CPC classification number: H05K1/14 ,  H01L23/3128 ,  H01L24/10 ,  H05K1/11 ,  H05K1/181 ,  H05K1/184 ,  H05K3/303 ,  H05K3/34 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H05K1/185 ,  H05K3/363 ,  H05K3/4007 ,  Y10T29/49165 ,  H01L2224/1191 ,  H01L23/3171 ,  H05K3/3436 ,  H01L2224/13021 ,  H01L2224/13022 ,  H05K2201/10515 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/16111 ,  H05K2201/10977 ,  H05K2203/043 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01079

Abstract: A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A

公开(公告)号：US09984993B2

公开(公告)日：2018-05-29

申请号：US15294508

申请日：2016-10-14

Applicant: Advanced Semiconductor, Inc.

Inventor： Min-Fong Shu ,  Yi-Hsiu Tseng ,  Kuan-Neng Chen ,  Shu-Chiao Kuo

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/1182 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13676 ,  H01L2224/13678 ,  H01L2224/13687 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81096 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81898 ,  H01L2224/83104 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/8109 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053

Abstract: A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.

公开(公告)号：US20160240503A1

公开(公告)日：2016-08-18

申请号：US14622494

申请日：2015-02-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Min-Fong Shu ,  Yi-Hsiu TSENG ,  Kuan-Neng CHEN ,  Shu-Chiao KUO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/1182 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13676 ,  H01L2224/13678 ,  H01L2224/13687 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81096 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81898 ,  H01L2224/83104 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/8109 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053

Abstract: The present disclosure relates to bonding structures useful in semiconductor packages and methods of manufacturing the same. In an embodiment, the bonding structure comprises a substrate, having a top surface and including at least one bonding pad, wherein each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface; and a semiconductor element including at least one pillar, wherein each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.

Abstract translation: 本公开涉及可用于半导体封装的结合结构及其制造方法。 在一个实施例中，接合结构包括具有顶表面并且包括至少一个焊盘的衬底，其中每个接合焊盘邻近衬底的顶表面设置并具有倾斜表面; 以及包括至少一个柱的半导体元件，其中每个柱结合到相应焊盘的倾斜表面的一部分，并且在所述柱的侧壁和相应的焊盘的倾斜表面之间形成间隙。

公开(公告)号：US09171814B2

公开(公告)日：2015-10-27

申请号：US14645289

申请日：2015-03-11

Applicant: Renesas Electronics Corporation

Inventor： Masaki Watanabe ,  Shinji Baba ,  Muneharu Tokunaga ,  Toshihiro Iwasaki

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10175 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17134 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.

公开(公告)号：US08441809B2

公开(公告)日：2013-05-14

申请号：US13161538

申请日：2011-06-16

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/78 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US20130026628A1

公开(公告)日：2013-01-31

申请号：US13645397

申请日：2012-10-04

Applicant: STATS CHIPPAC, LTD.

Inventor： Rajendra D. Pendse

IPC: H01L21/60 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract translation: 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹

公开(公告)号：US08064224B2

公开(公告)日：2011-11-22

申请号：US12059133

申请日：2008-03-31

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/78 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。