公开(公告)号：US20240079358A1

公开(公告)日：2024-03-07

申请号：US17939880

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Siva Sai Kishore Palli ,  Venkata Rama Satya Pradeep Vempaty ,  Wen How Sim ,  Chen Yu Huang ,  Harjashan Veer Singh

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05573 ,  H01L2224/16014 ,  H01L2224/1607 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/384

Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate and a die stack carried by the package substrate. The die stack can include at least a first semiconductor die carried by the package substrate, a second semiconductor die carried by the first semiconductor die. The first semiconductor die can have an upper surface and a first bond pad carried by the upper surface that includes a curvilinear concave depression formed in an uppermost surface of the first bond pad. The second semiconductor die has a lower surface and a second bond pad carried by the lower surface. The die stack can also include solder structure electrically coupling the first and second bond pads and at least partially filling the curvilinear concave depression formed in the uppermost surface of the first bond pad.