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公开(公告)号：US20240363572A1
公开(公告)日：2024-10-31
申请号：US18771523
申请日：2024-07-12
申请人： ROHM CO., LTD.
发明人： Akinori NII
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/16 , H01L2224/05015 , H01L2224/05073 , H01L2224/05155 , H01L2224/05582 , H01L2224/05644 , H01L2224/05664 , H01L2224/06051 , H01L2224/13083 , H01L2224/13147 , H01L2224/1357 , H01L2224/1403 , H01L2224/16245 , H01L2924/384
摘要： A semiconductor device includes a semiconductor element, conductive member connected to the semiconductor element, first metal layer and second metal layer. The semiconductor element includes element obverse/reverse surfaces opposite from each other in thickness direction, and first/second electrode terminals on the element obverse surface. The first metal layer is on the conductive member and bonded to the first electrode terminal. The second metal layer is on the conductive member and bonded to the second electrode terminal. The first electrode terminal includes a first bonding surface facing the first metal layer. The second electrode terminal includes a second bonding surface facing the second metal layer. The first bonding surface is smaller in area than the second bonding surface. The difference between representative lengths of the first metal layer and the first bonding surface is smaller than the difference between representative lengths of the second metal layer and the second bonding surface.
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公开(公告)号：US12087718B2
公开(公告)日：2024-09-10
申请号：US18300493
申请日：2023-04-14
发明人： Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen , Yen-Liang Lin
CPC分类号： H01L24/13 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05572 , H01L2224/05599 , H01L2224/10145 , H01L2224/11849 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13018 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/14051 , H01L2224/1412 , H01L2224/14152 , H01L2224/14153 , H01L2224/16056 , H01L2224/16059 , H01L2224/16238 , H01L2224/81191 , H01L2224/81345 , H01L2224/81815 , H01L2924/01322 , H01L2924/2064 , H01L2924/384 , Y10T428/12493 , Y10T428/24479
摘要： The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.
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公开(公告)号：US20240105657A1
公开(公告)日：2024-03-28
申请号：US18240273
申请日：2023-08-30
发明人： Hansung Ryu , Yongsung Park , Jongbeom Park , Junho Lee , Jihyun Lee
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/16 , H01L2224/13013 , H01L2224/13014 , H01L2224/13113 , H01L2224/13541 , H01L2224/13583 , H01L2224/16145 , H01L2224/16227 , H01L2924/384
摘要： A semiconductor package includes a first substrate, a first bonding pad on the first substrate, a solder ball on the first bonding pad, and a blocking layer on the solder ball, wherein a thickness of the blocking layer varies in a direction away from the first substrate.
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公开(公告)号：US20230253355A1
公开(公告)日：2023-08-10
申请号：US18300493
申请日：2023-04-14
发明人： Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen , Yen-Liang Lin
CPC分类号： H01L24/13 , H01L24/14 , H01L24/11 , H01L25/50 , H01L24/16 , H01L24/81 , H01L2924/2064 , H01L2924/384 , H01L2224/13012 , H01L2224/05552 , H01L2224/81345 , H01L2224/11849 , H01L2224/13018 , H01L2224/14152 , H01L2224/14153 , H01L2924/01322 , Y10T428/24479 , Y10T428/12493 , H01L2224/05572 , H01L2924/00014 , H01L2224/81815 , H01L2224/81191 , H01L2224/16238 , H01L2224/13147 , H01L2224/131 , H01L2224/13083 , H01L2224/13082 , H01L2224/05599 , H01L2224/0401 , H01L2224/13011 , H01L2224/13015 , H01L2224/14051 , H01L2224/10145 , H01L2224/1412
摘要： The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.
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公开(公告)号：US09953948B2
公开(公告)日：2018-04-24
申请号：US15363943
申请日：2016-11-29
发明人： Cheng-Chieh Hsieh , Cheng-Lin Huang , Po-Hao Tsai , Shang-Yun Hou , Jing-Cheng Lin , Shin-Puu Jeng
IPC分类号： H01L23/00 , H01L25/00 , H01L25/065
CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/1132 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11474 , H01L2224/1148 , H01L2224/11616 , H01L2224/11825 , H01L2224/11849 , H01L2224/1191 , H01L2224/13013 , H01L2224/13015 , H01L2224/13018 , H01L2224/13019 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1362 , H01L2224/13655 , H01L2224/13671 , H01L2224/13672 , H01L2224/16056 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/81121 , H01L2224/81143 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06555 , H01L2225/06565 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/12 , H01L2924/14 , H01L2924/3512 , H01L2924/35121 , H01L2924/384 , H01L2924/3841 , H01L2924/00014
摘要： A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
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公开(公告)号：US20170170135A1
公开(公告)日：2017-06-15
申请号：US15445058
申请日：2017-02-28
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L23/562 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05666 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11901 , H01L2224/13005 , H01L2224/13013 , H01L2224/13023 , H01L2224/1308 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/13655 , H01L2224/13666 , H01L2224/13671 , H01L2224/13684 , H01L2224/16235 , H01L2224/81815 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/2064 , H01L2924/351 , H01L2924/35121 , H01L2924/37001 , H01L2924/384 , Y10T156/10 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions
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公开(公告)号：US09633937B2
公开(公告)日：2017-04-25
申请号：US14778128
申请日：2014-12-16
申请人： Intel Corporation
发明人： Huiyang Fei , Prasanna Raghavan
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/498 , H01L23/13 , H01L23/16 , H01L25/065 , H01L25/18 , H01L25/00 , H01L21/48 , H01L21/56 , H01L23/29 , H01L23/31 , H01L23/00
CPC分类号： H01L23/49833 , H01L21/4853 , H01L21/565 , H01L23/13 , H01L23/16 , H01L23/293 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49883 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06572 , H01L2924/14 , H01L2924/1436 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/37001 , H01L2924/384 , H01L2924/014 , H01L2924/00014
摘要： The electronic package includes a substrate and an electronic component mounted to a surface of the substrate. An interposer is mounted to the surface of the substrate such that the interposer surrounds the electronic component and is electrically connected to the substrate. An over-mold covers the electronic component. In other forms, the example electronic package may be incorporated into an electronic assembly. The electronic assembly further includes a second electronic component mounted to the interposer. As an example, the second electronic component may be mounted to the interposer using solder bumps. It should be noted that any technique that is known now, or discovered in the future, may be used to mount the second electronic component to the interposer.
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8.发明申请公开(公告)号：US20160086910A1
公开(公告)日：2016-03-24
申请号：US14964096
申请日：2015-12-09
发明人： Young Do Kweon , Tongbi Jiang
IPC分类号： H01L23/00
CPC分类号： H01L24/742 , H01L21/4853 , H01L21/563 , H01L21/566 , H01L21/78 , H01L23/3114 , H01L23/49816 , H01L23/544 , H01L24/11 , H01L24/12 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/94 , H01L2223/54426 , H01L2223/54453 , H01L2223/54486 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/05569 , H01L2224/0557 , H01L2224/05571 , H01L2224/11013 , H01L2224/11015 , H01L2224/1183 , H01L2224/1184 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2224/274 , H01L2224/7598 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/384 , H01L2924/00 , H01L2224/05599
摘要： Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.
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公开(公告)号：US20160049340A1
公开(公告)日：2016-02-18
申请号：US14460805
申请日：2014-08-15
发明人： Vidhya Ramachandran , Urmi Ray
CPC分类号： H01L22/14 , G01B7/16 , G01B2210/56 , H01L22/34 , H01L23/3121 , H01L23/481 , H01L23/562 , H01L24/17 , H01L24/81 , H01L2224/023 , H01L2224/16227 , H01L2224/73257 , H01L2224/81191 , H01L2224/81908 , H01L2924/01049 , H01L2924/0105 , H01L2924/0549 , H01L2924/14 , H01L2924/19107 , H01L2924/35 , H01L2924/3511 , H01L2924/384
摘要： In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data.
摘要翻译： 在特定实施例中，一种装置包括位于半导体器件的第一侧上的应力传感器。 该装置还包括位于半导体器件的第二侧上的电路。 应力传感器被配置为检测半导体器件处的应力。 在另一个具体实施例中，一种方法包括从位于封装半导体器件的第一侧上的应力传感器接收数据。 封装的半导体器件包括位于封装的半导体器件的第二侧上的电路。 数据表示应力传感器检测到的应力。 该方法还包括基于该数据执行与封装半导体器件相关联的测试。
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公开(公告)号：US20150187720A1
公开(公告)日：2015-07-02
申请号：US14645289
申请日：2015-03-11
IPC分类号： H01L23/00 , H01L23/498 , H01L23/31
CPC分类号： H01L24/16 , H01L21/563 , H01L23/3157 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/10175 , H01L2224/11462 , H01L2224/11849 , H01L2224/13013 , H01L2224/13014 , H01L2224/13111 , H01L2224/13147 , H01L2224/16055 , H01L2224/1607 , H01L2224/16113 , H01L2224/16147 , H01L2224/16225 , H01L2224/16238 , H01L2224/17134 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81007 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2224/831 , H01L2224/83192 , H01L2224/83862 , H01L2224/9211 , H01L2224/92125 , H01L2924/0665 , H01L2924/15311 , H01L2924/181 , H01L2924/384 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.
摘要翻译： 以提高半导体器件的倒装芯片接合中的耦合可靠性。 通过在制造半导体器件中使用布线基板，其中布线基板的上表面上穿过阻焊膜的开口区域的布线在布线的一侧上具有凸块电极， 另一方面，在其上没有凸起电极的多个宽幅部分上，在焊料预涂工序的回流处理期间，布线上的焊料可以分散到每个宽幅部分。 通过这样的结构，能够减少各宽端部的端子上的焊料和焊料之间的高度差，并且提高倒装芯片接合时的耦合可靠性。
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