公开(公告)号：US09818679B2

公开(公告)日：2017-11-14

申请号：US14871742

申请日：2015-09-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Toshihiro Iwasaki ,  Masaki Watanabe

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/50

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

公开(公告)号：US09171791B2

公开(公告)日：2015-10-27

申请号：US14249097

申请日：2014-04-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Toshihiro Iwasaki ,  Masaki Watanabe

IPC: H01L23/498 ,  H01L23/50 ,  H01L25/10

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Abstract translation: 本发明提供作为低成本倒装芯片BGA的多引脚半导体器件。 在倒装芯片BGA中，多层布线基板的上表面的周边区域中的多个信号接合电极被分离为内部和外部的多个信号接合电极，并且耦合到多个内部的信号布线耦合的多个信号通孔是 位于多行信号键合电极和多个核心电源用接合电极之间的中心区域，使得可以减小芯片焊盘间距，并且能够在不增加数量的情况下降低BGA的成本 的多层布线基板中的层。

公开(公告)号：US11217670B2

公开(公告)日：2022-01-04

申请号：US16722355

申请日：2019-12-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuji Takahashi ,  Masaki Watanabe ,  Masashi Sahara ,  Kentaro Yamada ,  Masaki Sakashita ,  Shinichi Maeda ,  Yoshiaki Yamada

IPC: H01L29/417 ,  H01L29/732 ,  H01L21/324 ,  H01L29/40 ,  H01L21/02 ,  H01L29/47

Abstract: A characteristic of a semiconductor device having a back electrode including an Au—Sb alloy is improved. The semiconductor device has a semiconductor substrate and the back electrode including the Au—Sb alloy layer. The back electrode is formed on the semiconductor substrate. The Sb concentration in the Au—Sb alloy layer is equal to or greater than 15 wt %, and equal to or less than 37 wt %. The thickness of the Au—Sb alloy layer is equal to or larger than 20 nm, and equal to or less than 45 nm.

公开(公告)号：US10134663B2

公开(公告)日：2018-11-20

申请号：US15714801

申请日：2017-09-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Toshihiro Iwasaki ,  Masaki Watanabe

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/50

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

公开(公告)号：US20180012831A1

公开(公告)日：2018-01-11

申请号：US15714801

申请日：2017-09-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji BABA ,  Toshihiro IWASAKI ,  Masaki Watanabe

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/50

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

公开(公告)号：US20160111388A1

公开(公告)日：2016-04-21

申请号：US14983753

申请日：2015-12-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Masaki Watanabe ,  Muneharu Tokunaga ,  Kazuyuki Nakagawa

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/1134 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，作为安装有半导体芯片的布线基板，不使用积层布线板，而是使用贯通布线板THWB。 以这种方式，在本发明中，仅使用芯层形成的贯通布线板，因此不需要考虑堆积层与芯层之间的热膨胀系数的差异， 不需要考虑由于积聚层不存在而在积层中形成的精细通孔的电断开。 结果，根据本发明，可以提高半导体器件的可靠性，同时降低成本。

公开(公告)号：US20160027723A1

公开(公告)日：2016-01-28

申请号：US14871742

申请日：2015-09-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji BABA ,  Toshihiro IWASAKI ,  Masaki Watanabe

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/50

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Abstract translation: 本发明提供作为低成本倒装芯片BGA的多引脚半导体器件。 在倒装芯片BGA中，多层布线基板的上表面的周边区域中的多个信号接合电极被分离为内部和外部的多个信号接合电极，并且耦合到多个内部的信号布线耦合的多个信号通孔是 位于多行信号键合电极和多个核心电源用接合电极之间的中心区域，使得可以减小芯片焊盘间距，并且能够在不增加数量的情况下降低BGA的成本 的多层布线基板中的层。

公开(公告)号：US09171814B2

公开(公告)日：2015-10-27

申请号：US14645289

申请日：2015-03-11

Applicant: Renesas Electronics Corporation

Inventor： Masaki Watanabe ,  Shinji Baba ,  Muneharu Tokunaga ,  Toshihiro Iwasaki

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10175 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17134 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.

公开(公告)号：US08963327B2

公开(公告)日：2015-02-24

申请号：US13872012

申请日：2013-04-26

Applicant: Renesas Electronics Corporation

Inventor： Kozo Harada ,  Shinji Baba ,  Masaki Watanabe ,  Satoshi Yamada

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/50

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14152 ,  H01L2224/14154 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes lands having an NSMD (non-solder mask defined) structure for mounting thereon solder balls placed in an inner area of a chip mounting area. The lands for mounting thereon solder balls are placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view. The semiconductor device is mounted on a mounting substrate with the balls.

Abstract translation: 半导体器件包括具有用于安装在芯片安装区域的内部区域中的焊球的NSMD（非阻焊掩模限定）结构的焊盘。 用于安装焊锡球的焊盘放置在平面图中与芯片安装区域重叠的通孔布线板的背面的区域中。 半导体器件安装在具有球的安装基板上。

公开(公告)号：US10098179B2

公开(公告)日：2018-10-09

申请号：US14258246

申请日：2014-04-22

Applicant: Renesas Electronics Corporation

Inventor： Shintaro Yamamichi ,  Hirokazu Honda ,  Masaki Watanabe ,  Junichi Arita ,  Norio Okada ,  Jun Ueno ,  Masashi Nishimoto ,  Michitaka Kimura ,  Tomohiro Nishiyama

IPC: H04B1/38 ,  H04B1/40 ,  H04W84/18

Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).