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Patent Agency Ranking
公开(公告)号：US20160111388A1
公开(公告)日：2016-04-21
申请号：US14983753
申请日：2015-12-30
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shinji Baba , Masaki Watanabe , Muneharu Tokunaga , Kazuyuki Nakagawa
IPC: H01L23/00 , H01L23/31 , H01L23/29 , H01L23/498
CPC classification number: H01L24/17 , H01L21/563 , H01L23/291 , H01L23/3135 , H01L23/3142 , H01L23/3171 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/81 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/1134 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/13075 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/14136 , H01L2224/14155 , H01L2224/14177 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/83102 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/3512 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.
Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，作为安装有半导体芯片的布线基板，不使用积层布线板，而是使用贯通布线板THWB。 以这种方式，在本发明中，仅使用芯层形成的贯通布线板，因此不需要考虑堆积层与芯层之间的热膨胀系数的差异， 不需要考虑由于积聚层不存在而在积层中形成的精细通孔的电断开。 结果，根据本发明，可以提高半导体器件的可靠性，同时降低成本。
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公开(公告)号：US09171814B2
公开(公告)日：2015-10-27
申请号：US14645289
申请日：2015-03-11
Applicant: Renesas Electronics Corporation
Inventor： Masaki Watanabe , Shinji Baba , Muneharu Tokunaga , Toshihiro Iwasaki
IPC: H01L23/522 , H01L23/00 , H01L23/31 , H01L23/498
CPC classification number: H01L24/16 , H01L21/563 , H01L23/3157 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/10175 , H01L2224/11462 , H01L2224/11849 , H01L2224/13013 , H01L2224/13014 , H01L2224/13111 , H01L2224/13147 , H01L2224/16055 , H01L2224/1607 , H01L2224/16113 , H01L2224/16147 , H01L2224/16225 , H01L2224/16238 , H01L2224/17134 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81007 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2224/831 , H01L2224/83192 , H01L2224/83862 , H01L2224/9211 , H01L2224/92125 , H01L2924/0665 , H01L2924/15311 , H01L2924/181 , H01L2924/384 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2224/81 , H01L2224/83 , H01L2924/00
Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.
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公开(公告)号：US20150187720A1
公开(公告)日：2015-07-02
申请号：US14645289
申请日：2015-03-11
Applicant: Renesas Electronics Corporation
Inventor： Masaki Watanabe , Shinji Baba , Muneharu Tokunaga , Toshihiro Iwasaki
IPC: H01L23/00 , H01L23/498 , H01L23/31
CPC classification number: H01L24/16 , H01L21/563 , H01L23/3157 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/10175 , H01L2224/11462 , H01L2224/11849 , H01L2224/13013 , H01L2224/13014 , H01L2224/13111 , H01L2224/13147 , H01L2224/16055 , H01L2224/1607 , H01L2224/16113 , H01L2224/16147 , H01L2224/16225 , H01L2224/16238 , H01L2224/17134 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81007 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2224/831 , H01L2224/83192 , H01L2224/83862 , H01L2224/9211 , H01L2224/92125 , H01L2924/0665 , H01L2924/15311 , H01L2924/181 , H01L2924/384 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2224/81 , H01L2224/83 , H01L2924/00
Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.
Abstract translation: 以提高半导体器件的倒装芯片接合中的耦合可靠性。 通过在制造半导体器件中使用布线基板，其中布线基板的上表面上穿过阻焊膜的开口区域的布线在布线的一侧上具有凸块电极， 另一方面，在其上没有凸起电极的多个宽幅部分上，在焊料预涂工序的回流处理期间，布线上的焊料可以分散到每个宽幅部分。 通过这样的结构，能够减少各宽端部的端子上的焊料和焊料之间的高度差，并且提高倒装芯片接合时的耦合可靠性。
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公开(公告)号：US08994175B2
公开(公告)日：2015-03-31
申请号：US14139948
申请日：2013-12-24
Applicant: Renesas Electronics Corporation
Inventor： Masaki Watanabe , Shinji Baba , Muneharu Tokunaga , Toshihiro Iwasaki
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L24/16 , H01L21/563 , H01L23/3157 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/10175 , H01L2224/11462 , H01L2224/11849 , H01L2224/13013 , H01L2224/13014 , H01L2224/13111 , H01L2224/13147 , H01L2224/16055 , H01L2224/1607 , H01L2224/16113 , H01L2224/16147 , H01L2224/16225 , H01L2224/16238 , H01L2224/17134 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81007 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2224/831 , H01L2224/83192 , H01L2224/83862 , H01L2224/9211 , H01L2224/92125 , H01L2924/0665 , H01L2924/15311 , H01L2924/181 , H01L2924/384 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2224/81 , H01L2224/83 , H01L2924/00
Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.
Abstract translation: 以提高半导体器件的倒装芯片接合中的耦合可靠性。 通过在制造半导体器件中使用布线基板，其中布线基板的上表面上穿过阻焊膜的开口区域的布线在布线的一侧上具有凸块电极， 另一方面，在其上没有凸起电极的多个宽幅部分上，在焊料预涂工序的回流处理期间，布线上的焊料可以分散到每个宽幅部分。 通过这样的结构，能够减少各宽端部的端子上的焊料和焊料之间的高度差，并且提高倒装芯片接合时的耦合可靠性。
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公开(公告)号：US20140284789A1
公开(公告)日：2014-09-25
申请号：US14139948
申请日：2013-12-24
Applicant: Renesas Electronics Corporation
Inventor： Masaki Watanabe , Shinji Baba , Muneharu Tokunaga , Toshihiro Iwasaki
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L24/16 , H01L21/563 , H01L23/3157 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/10175 , H01L2224/11462 , H01L2224/11849 , H01L2224/13013 , H01L2224/13014 , H01L2224/13111 , H01L2224/13147 , H01L2224/16055 , H01L2224/1607 , H01L2224/16113 , H01L2224/16147 , H01L2224/16225 , H01L2224/16238 , H01L2224/17134 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81007 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2224/831 , H01L2224/83192 , H01L2224/83862 , H01L2224/9211 , H01L2224/92125 , H01L2924/0665 , H01L2924/15311 , H01L2924/181 , H01L2924/384 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2224/81 , H01L2224/83 , H01L2924/00
Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.
Abstract translation: 以提高半导体器件的倒装芯片接合中的耦合可靠性。 通过在制造半导体器件中使用布线基板，其中布线基板的上表面上穿过阻焊膜的开口区域的布线在布线的一侧上具有凸块电极， 另一方面，在其上没有凸起电极的多个宽幅部分上，在焊料预涂工序的回流处理期间，布线上的焊料可以分散到每个宽幅部分。 通过这样的结构，能够减少各宽端部的端子上的焊料和焊料之间的高度差，并且提高倒装芯片接合时的耦合可靠性。
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