公开(公告)号：US09496235B2

公开(公告)日：2016-11-15

申请号：US14466877

申请日：2014-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1362 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16056 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Abstract translation: 提供了一种用于导电柱的系统和方法。 一个实施例包括具有位于其外边缘周围的沟槽的导电柱。 当在导电柱上形成导电凸块时，沟槽用于引导诸如焊料的导电材料。 导电柱然后可以通过导电材料电连接到另一接触件。

公开(公告)号：US11682644B2

公开(公告)日：2023-06-20

申请号：US17361950

申请日：2021-06-29

Applicant: Infineon Technologies AG

Inventor： Swee Kah Lee ,  Sook Woon Chan ,  Fong Mei Lum ,  Joachim Mahler ,  Muhammad Muhammat Sanusi

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/11822 ,  H01L2224/1357 ,  H01L2224/1362 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/13638 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/81801

Abstract: A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

公开(公告)号：US20160368104A1

公开(公告)日：2016-12-22

申请号：US15120937

申请日：2015-02-19

Applicant: KOKI COMPANY LIMITED

Inventor： Atsushi Irisawa ,  Rie Wada

IPC: B23K35/26 ,  H01L23/00 ,  B23K35/36

CPC classification number: B23K35/262 ,  B23K35/0222 ,  B23K35/26 ,  B23K35/36 ,  B23K2101/40 ,  C22C13/02 ,  H01L24/16 ,  H01L2224/13611 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2924/01032 ,  H01L2924/014 ,  H05K3/3463

Abstract: Provided are a lead-free solder alloy which consists of Sb in an amount of more than 3.0% but 10% or less by mass, and the balance including Sn, and others.

Abstract translation: 本发明提供一种无铅焊料合金，其含量大于3.0％但为10质量％以下，余量为Sn等。

公开(公告)号：US20140361432A1

公开(公告)日：2014-12-11

申请号：US14466877

申请日：2014-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1362 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16056 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Abstract translation: 提供了一种用于导电柱的系统和方法。 一个实施例包括具有位于其外边缘周围的沟槽的导电柱。 当在导电柱上形成导电凸块时，沟槽用于引导诸如焊料的导电材料。 导电柱然后可以通过导电材料电连接到另一接触件。

公开(公告)号：US20240038707A1

公开(公告)日：2024-02-01

申请号：US17875778

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Cassie M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/13019 ,  H01L2224/13582 ,  H01L2224/81815 ,  H01L2224/13147 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13124 ,  H01L2224/13184 ,  H01L2224/13157 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/1369 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13613 ,  H01L2224/13609 ,  H01L2224/13618 ,  H01L2224/1362

Abstract: In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

公开(公告)号：US09764430B2

公开(公告)日：2017-09-19

申请号：US15120937

申请日：2015-02-19

Applicant: KOKI Company Limited

Inventor： Atsushi Irisawa ,  Rie Wada

IPC: H01L23/14 ,  B23K35/36 ,  B23K35/26 ,  B23K35/02 ,  C22C13/02 ,  H05K3/34 ,  H01L23/00 ,  B23K101/40

CPC classification number: B23K35/262 ,  B23K35/0222 ,  B23K35/26 ,  B23K35/36 ,  B23K2101/40 ,  C22C13/02 ,  H01L24/16 ,  H01L2224/13611 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2924/01032 ,  H01L2924/014 ,  H05K3/3463

Abstract: Provided are a lead-free solder alloy which consists of Sb in an amount of more than 3.0% but 10% or less by mass, and the balance including Sn, and others.

公开(公告)号：US20170084571A1

公开(公告)日：2017-03-23

申请号：US15363943

申请日：2016-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1362 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16056 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

公开(公告)号：US09269683B2

公开(公告)日：2016-02-23

申请号：US14200613

申请日：2014-03-07

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/12 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract translation: 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US20020090756A1

公开(公告)日：2002-07-11

申请号：US09969657

申请日：2001-10-04

Inventor： Masamoto Tago ,  Yoshihiro Tomita ,  Kenji Takahashi

IPC: H01L021/48 ,  H01L021/44 ,  H01L023/48

CPC classification number: H01L24/13 ,  H01L23/481 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1362 ,  H01L2224/13664 ,  H01L2224/45144 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/8383 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2224/05144 ,  H01L2224/05155

Abstract: A semiconductor device includes a semiconductor chip. A substrate is arranged in opposition to the semiconductor chip. A first electrode is placed on the semiconductor chip while a second electrode is placed on the substrate. An intermetallic compound layer is arranged between the first electrode and the second electrode. Each of the first and second electrodes is made of predetermined electrode material. The intermetallic compound layer is made of the electrode material and bonding material supplied to at least one of the first and second electrodes.

Abstract translation: 半导体器件包括半导体芯片。 衬底被布置成与半导体芯片相对。 将第一电极放置在半导体芯片上，同时将第二电极放置在基板上。 金属间化合物层布置在第一电极和第二电极之间。 第一和第二电极中的每一个由预定的电极材料制成。 金属间化合物层由提供给第一和第二电极中的至少一个的电极材料和接合材料制成。

公开(公告)号：US09761477B2

公开(公告)日：2017-09-12

申请号：US15286801

申请日：2016-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun-ho Chang ,  Un-byoung Kang ,  Tae-je Cho

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/36 ,  H01L21/768 ,  H01L21/304 ,  H01L23/544

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/36 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/5446 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/14519 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161

Abstract: Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.