公开(公告)号：US20240258286A1

公开(公告)日：2024-08-01

申请号：US18593536

申请日：2024-03-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Chieh-Yen Chen

IPC分类号： H01L25/16 ,  H01L23/00

CPC分类号： H01L25/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L2924/12 ,  H01L2924/1431 ,  H01L2924/1434

摘要： In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

公开(公告)号：US20180132347A1

公开(公告)日：2018-05-10

申请号：US15868773

申请日：2018-01-11

申请人： Nthdegree Technologies Worldwide Inc.

发明人： William Johnstone Ray ,  Richard Austin Blanchard ,  Mark David Lowenthal ,  Bradley Steven Oraw

IPC分类号： H05K1/02 ,  H01L23/00

CPC分类号： H05K1/0296 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/00 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/18 ,  H01L25/50 ,  H01L33/20 ,  H01L2221/68381 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/25105 ,  H01L2224/25174 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82143 ,  H01L2224/92244 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95115 ,  H01L2224/95143 ,  H01L2224/95146 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091

摘要： A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

公开(公告)号：US09806017B2

公开(公告)日：2017-10-31

申请号：US14589578

申请日：2015-01-05

申请人： Tessera, Inc.

发明人： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/50 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1047 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/15151 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15172 ,  H01L2924/15182 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

摘要： A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

公开(公告)号：US20170125372A1

公开(公告)日：2017-05-04

申请号：US15408930

申请日：2017-01-18

申请人： Nthdegree Technologies Worldwide Inc.

发明人： William Johnstone Ray ,  Richard Austin Blanchard ,  Mark David Lowenthal ,  Bradley Steven Oraw

IPC分类号： H01L23/00 ,  H01L25/18 ,  H01L25/07 ,  H01L25/00

CPC分类号： H01L24/95 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/18 ,  H01L25/50 ,  H01L33/20 ,  H01L2221/68381 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/25105 ,  H01L2224/25174 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82143 ,  H01L2224/92244 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95115 ,  H01L2224/95143 ,  H01L2224/95146 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H05K1/029 ,  H05K1/0296 ,  H05K3/12

摘要： A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

公开(公告)号：US09397057B2

公开(公告)日：2016-07-19

申请号：US14723738

申请日：2015-05-28

申请人： Kabushiki Kaisha Toshiba

发明人： Yutaka Onozuka ,  Hiroshi Yamada ,  Nobuto Managaki

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/04 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/532

CPC分类号： H01L24/08 ,  H01L21/76802 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/12

摘要： According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin.

摘要翻译： 根据实施例，半导体器件包括绝缘树脂，互连件，多个半导体元件，第一导电单元，第一连接器和第一金属层。 绝缘树脂包括第一区域和第二区域。 互连的至少一部分被布置成具有第一方向的第一区域的至少一部分。 第一导电单元沿第一方向刺穿第二区域。 第一连接器的至少一部分布置成具有第一导电单元的至少一部分在第一方向上。 第一连接器的至少一部分布置成具有与第一方向交叉的第二方向的互连的至少一部分。 第一金属层设置在第一导电单元和第一连接器之间。 第一金属层接触绝缘树脂。

公开(公告)号：US20150270243A1

公开(公告)日：2015-09-24

申请号：US14707983

申请日：2015-05-08

申请人： King Dragon International Inc.

发明人： Wen Kun Yang ,  Yu-Hsiang Yang

IPC分类号： H01L23/00 ,  H01L21/268 ,  H01L21/768 ,  H01L21/304

CPC分类号： H01L24/32 ,  H01L21/268 ,  H01L21/304 ,  H01L21/76802 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/544 ,  H01L24/00 ,  H01L24/09 ,  H01L24/16 ,  H01L24/20 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/03015 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0918 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/16113 ,  H01L2224/16221 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32221 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01014 ,  H01L2924/12 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

公开(公告)号：US20150270239A1

公开(公告)日：2015-09-24

申请号：US14223157

申请日：2014-03-24

申请人： King Dragon International Inc.

发明人： Wen Kun Yang ,  Yu-Hsiang Yang

IPC分类号： H01L23/00 ,  B81C1/00 ,  B81B7/00 ,  H01L23/538 ,  H01L23/544

CPC分类号： H01L24/32 ,  H01L21/268 ,  H01L21/304 ,  H01L21/76802 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/544 ,  H01L24/09 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/105 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/03015 ,  H01L2224/0401 ,  H01L2224/0918 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/16113 ,  H01L2224/16221 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2924/01014 ,  H01L2924/12 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

摘要翻译： 本发明提出了一种半导体器件封装结构，包括衬底，粘合剂层和管芯。 所述基板具有电气通孔，以分别在所述基板的顶表面和底表面上分别连接第一和第二布线电路，其中在所述第一布线电路上形成接触导电凸块。 底部填充粘合剂层形成在除了模具的区域之外的基板的顶表面和第一布线电路上。 所述管芯在所述管芯的接合焊盘上具有凸起结构，其中所述管芯的所述突起结构电连接到所述衬底的第一布线电路的接触导电凸块。

公开(公告)号：US20150194403A1

公开(公告)日：2015-07-09

申请号：US14663755

申请日：2015-03-20

申请人： MediaTek Inc

发明人： Kuei-Ti CHAN ,  Tzu-Hung LIN ,  Ching-Liou HUANG

IPC分类号： H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/64 ,  H01L23/66

CPC分类号： H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

摘要： A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.

摘要翻译： 半导体封装包括衬底，设置在衬底上的第一钝化层和设置在第一钝化层上的凸块下金属层。 无源器件设置在凸块下金属层上，并且附加的凸块下金属层设置在与凸块下金属层隔离的第一钝化层上。 导电柱设置在另外的凸块下金属层上，其中导电柱和无源器件处于同一水平。

公开(公告)号：US09029990B2

公开(公告)日：2015-05-12

申请号：US13734246

申请日：2013-01-04

申请人： Texas Instruments Incorporated

发明人： Lee Hang Meng@Eugene Lee ,  Anis Fauzi Abdul Aziz ,  Yien Sien Khoo

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/97 ,  H01L2924/12 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/81

摘要： An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.

摘要翻译： 一种集成电路（IC）封装，包括底部引线框架，安装在底部引线框架上的插入器，安装在插入器上的倒装芯片模块和电连接到插入器的顶部引线框架。 此外，制造集成电路（IC）封装的方法包括将裸片电连接和物理附接到插入器，将插入件附接到底部引线框架，将分立电路部件附接到插入器并将顶部引线框架附接到底部引线框架。

公开(公告)号：US20150123254A1

公开(公告)日：2015-05-07

申请号：US14523066

申请日：2014-10-24

申请人： SFI Electronics Technology Inc.

发明人： Ching-Hohn LIEN ,  Xing- Xiang HUANG ,  Hsing-Tsai HUANG ,  Hong-Zong XU

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/9221 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/48

摘要： A novel chip scale diode package due to no containing outer lead pins is miniaturized like a chip scale appearance to promote dimensional accuracy so that the diode package is so suitably produced by automation equipment to get automated mass production; the produced diode package may contain one or more diode chips to increase versatile functions more useful in applications, such as produced as a SMT diode package or an array-type SMT diode, and the present diode package due to made of no lead-containing material conforms to requirements for environmental protection.

摘要翻译： 由于不含外部引脚引脚的新颖的芯片尺寸二极管封装小型化，像芯片尺寸外观，以提高尺寸精度，使得二极管封装由自动化设备适当地生产以获得自动批量生产; 所生成的二极管封装可以包含一个或多个二极管芯片，以增加在应用中更有用的通用功能，例如作为SMT二极管封装或阵列型SMT二极管制造的，以及由于不含含铅材料制成的本二极管封装 符合环保要求。