公开(公告)号：US20240282685A1

公开(公告)日：2024-08-22

申请号：US18682829

申请日：2022-08-10

申请人： LG INNOTEK CO., LTD.

发明人： Jae Hun JEONG ,  Jong Bae SHIN ,  Soo Min LEE

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49822 ,  H01L21/481 ,  H01L23/49838 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/13101 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/16227 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/32227 ,  H01L2924/01048 ,  H01L2924/014

摘要： A circuit board according to an embodiment includes a first insulating layer, a first circuit pattern layer disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer and the first circuit pattern layer, wherein the second insulating layer includes a first region including a cavity and a second region excluding the first region, wherein the first region of the second insulating layer includes a first portion concave toward a lower surface of the second insulating layer, and a second portion convex toward an upper surface of the second insulating layer.

公开(公告)号：US12021037B2

公开(公告)日：2024-06-25

申请号：US18077778

申请日：2022-12-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/5386 ,  H01L24/17 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/81815 ,  H01L2924/00014

摘要： Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.

公开(公告)号：US20240194572A1

公开(公告)日：2024-06-13

申请号：US18444651

申请日：2024-02-17

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Kyoung Yeon LEE ,  Byong Jin KIM ,  Jae Min BAE ,  Hyung Il JEON ,  Gi Jeong KIM ,  Ji Young CHUNG

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/49548 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49861 ,  H01L2021/60007 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/181

摘要： A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.

公开(公告)号：US11908779B2

公开(公告)日：2024-02-20

申请号：US17233778

申请日：2021-04-19

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Kyoung Yeon Lee ,  Byong Jin Kim ,  Jae Min Bae ,  Hyung Il Jeon ,  Gi Jeong Kim ,  Ji Young Chung

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/60 ,  H01L23/00

CPC分类号： H01L23/49548 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2021/60007 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.

公开(公告)号：US11798906B2

公开(公告)日：2023-10-24

申请号：US17551548

申请日：2021-12-15

申请人： Samsung Electronics Co., Ltd.

发明人： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-Jin Lee

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0221 ,  H01L2224/02126 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

摘要： A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US20230230962A1

公开(公告)日：2023-07-20

申请号：US18190341

申请日：2023-03-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Chung-Shi Liu

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L24/81 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/81007 ,  H01L2224/81801 ,  H01L2224/81948 ,  H01L2224/81947 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/13147 ,  H01L24/13 ,  H01L2224/11462 ,  H01L2224/05571 ,  H01L2924/381 ,  H01L2224/13101 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16145 ,  H01L2224/81141 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/81815 ,  H01L2924/14 ,  H01L2224/05558

摘要： An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

公开(公告)号：US11677059B2

公开(公告)日：2023-06-13

申请号：US17223592

申请日：2021-04-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ji-hoon Yun ,  Jong-sup Song ,  Seol-young Choi

IPC分类号： H01L33/62 ,  H01L33/48 ,  H01L33/50 ,  H01L33/60 ,  H01L23/00 ,  H01L27/02 ,  H01L29/866

CPC分类号： H01L33/62 ,  H01L24/16 ,  H01L24/17 ,  H01L33/486 ,  H01L33/502 ,  H01L33/60 ,  H01L24/13 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/866 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/16257 ,  H01L2224/17106 ,  H01L2224/81011 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12041 ,  H01L2924/3512 ,  H01L2933/0033

摘要： A light-emitting device package includes a lead frame, a light-emitting device chip, a molding structure, and a plurality of slots. The lead frame includes a first lead and a second lead including metal and spaced apart from each other. The light-emitting device chip is mounted on a first area of the lead frame, which includes a part of the first lead and a part of the second lead. The molding structure includes an outer barrier surrounding an outside of the lead frame and an inner barrier. The plurality of slots are formed in each of the first lead and the second lead. The inner barrier divides the lead from into the first area and a second area. The inner barrier fills between the first lead in the second lead. The second area is located outside of the first area. The plurality of slots are filled by the molding structure.

公开(公告)号：US11658137B2

公开(公告)日：2023-05-23

申请号：US17176574

申请日：2021-02-16

申请人： Chengwei Wu

发明人： Chengwei Wu

IPC分类号： H01L23/00 ,  H01L25/18 ,  H01L25/10 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/17 ,  H01L24/32 ,  H01L25/105 ,  H01L25/18 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1011 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/00014

摘要： A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved.

公开(公告)号：US20190200446A1

公开(公告)日：2019-06-27

申请号：US16329200

申请日：2016-09-28

申请人： Intel Corporation

发明人： Brian J. Long

IPC分类号： H05K1/02 ,  G06F1/20 ,  H05K7/20 ,  G06F1/18 ,  H05K1/18 ,  H05K1/14 ,  H05K3/36 ,  H01L23/367

CPC分类号： H05K1/0204 ,  G06F1/181 ,  G06F1/203 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4006 ,  H01L23/427 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15321 ,  H05K1/0209 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/144 ,  H05K1/181 ,  H05K3/36 ,  H05K7/20336 ,  H05K7/20818 ,  H05K2201/0367 ,  H05K2201/042 ,  H05K2201/064 ,  H05K2201/066 ,  H05K2201/1028 ,  H05K2201/1034 ,  H05K2201/10378 ,  H05K2201/10393 ,  H05K2201/10409 ,  H05K2201/10734 ,  H01L2924/014 ,  H01L2224/29099

摘要： Aspects of the embodiments include an edge card and methods of making the same. The edge card can include a printed circuit board (PCB) comprising a first end and a second end, the first end comprising a plurality of metal contact fingers configured to interface with an edge connector, and the second end comprising a through-hole configured to mate with a post of a screw, the PCB further comprising an aperture proximate the second end of the PCB. The PCB can also include a thermal conduction element secured to the PCB, the thermal conduction element supporting an integrated circuit package, the integrated circuit package received by the aperture, wherein the thermal conduction element contacts the PCB proximate the through-hole and the thermal conduction element is configured to conduct heat from the integrated circuit towards the second portion of the printed circuit board.

公开(公告)号：US20190044048A1

公开(公告)日：2019-02-07

申请号：US15891518

申请日：2018-02-08

申请人： Intel Corporation

发明人： Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo

IPC分类号： H01L39/14 ,  H01L39/22 ,  H01L29/12 ,  H01L29/15 ,  H01L29/423 ,  H01L29/40 ,  H01L39/24 ,  G06N99/00

CPC分类号： H01L39/146 ,  G06N10/00 ,  H01L23/445 ,  H01L23/46 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L29/127 ,  H01L29/151 ,  H01L29/401 ,  H01L29/42316 ,  H01L39/228 ,  H01L39/24 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

摘要： Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.