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公开(公告)号：US11907808B2
公开(公告)日：2024-02-20
申请号：US17464583
申请日：2021-09-01
申请人： Intel Corporation
发明人： Albert Schmitz , Anne Matsuura , Ravi Pillarisetty , Shavindra Premaratne , Justin Hogaboam , Lester Lampert
摘要： Apparatus and method for measurement-free (MF) quantum error correction (QEC). For example, one embodiment of a method comprises: determining an error syndrome on a first subset of ancilla qubits of a quantum processor; decoding the error syndrome to produce decoded results on a second subset of ancilla qubits of the quantum processor; applying the decoded results to one or more system qubits; and unconditionally resetting the first subset and/or second subset of ancilla qubits to remove entropy and/or noise from the quantum system, wherein the operations of determining the error syndrome, decoding the error syndrome, applying the error syndrome, and unconditionally resetting the first and/or second subset of ancilla qubits are performed responsive to a qubit controller executing quantum control instructions provided from or derived from a script and without transmitting measurement data related to the error syndrome to a non-quantum computing device.
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公开(公告)号：US11658212B2
公开(公告)日：2023-05-23
申请号：US16274572
申请日：2019-02-13
申请人： Intel Corporation
发明人： Hubert C. George , Ravi Pillarisetty , Lester Lampert , James S. Clarke , Nicole K. Thomas , Stephanie A. Bojarski , Roman Caudillo , David J. Michalak , Jeanette M. Roberts , Thomas Francis Watson
IPC分类号： H01L29/12 , H01L29/16 , G06N10/00 , H01L29/78 , H01L23/522
CPC分类号： H01L29/122 , G06N10/00 , H01L29/16 , H01L29/7851 , H01L23/5226
摘要： Disclosed herein are quantum dot devices with conductive liners, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base, a first fin extending from the base, a second fin extending from the base, a conductive material between the first fin and the second fin, and a dielectric material between the conductive material and the first fin.
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公开(公告)号：US10565515B2
公开(公告)日：2020-02-18
申请号：US16013384
申请日：2018-06-20
申请人： Intel Corporation
发明人： Lester Lampert , Ravi Pillarisetty , Nicole K. Thomas , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , James S. Clarke
摘要： Embodiments of the present disclosure describe quantum circuit assemblies utilizing triaxial cables to communicate signals to/from quantum circuit components. One assembly includes a cooling apparatus for cooling a quantum circuit component that includes at least one qubit device. The cooling apparatus includes at least one triaxial connector for providing signals to and/or receiving signals from the quantum circuit component using one or more triaxial cables. Other assemblies include quantum circuit components and various electronic components (e.g. attenuators, filters, or amplifiers) for use within the cooling apparatus, adapted to be used with triaxial cables by incorporating triaxial connectors as well.
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公开(公告)号：US10475912B2
公开(公告)日：2019-11-12
申请号：US15900655
申请日：2018-02-20
申请人： Intel Corporation
发明人： Nicole K. Thomas , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke , Willy Rachmady
IPC分类号： H01L39/00 , H01L29/778 , H01L29/78 , H01L29/51 , H01L29/66 , G06N10/00 , H01L39/02 , H01L29/82
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.
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公开(公告)号：US10388848B2
公开(公告)日：2019-08-20
申请号：US15924410
申请日：2018-03-19
申请人： Intel Corporation
发明人： Nicole K. Thomas , James S. Clarke , Jessica M. Torres , Lester Lampert , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , David J. Michalak
摘要： Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.
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公开(公告)号：US10347834B2
公开(公告)日：2019-07-09
申请号：US15928220
申请日：2018-03-22
申请人： INTEL CORPORATION
发明人： Nicole K. Thomas , Marko Radosavljevic , Sansaptak Dasgupta , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke
摘要： Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.
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公开(公告)号：US20190044668A1
公开(公告)日：2019-02-07
申请号：US15913026
申请日：2018-03-06
申请人： Intel Corporation
摘要： One aspect of the present disclosure provides a quantum circuit assembly that includes a substrate with one or more qubit devices, and at least one demultiplexer included in a single chip with the qubit device(s). The demultiplexer is configured to receive a combined signal from external electronics, the combined signal including a combination of a plurality of signals in different frequency ranges, and to demultiplex said plurality of signals within the combined signal. The demultiplexer is further configured to apply different demultiplexed signals to different lines of a single qubit device, or/and to different qubit devices. Providing such demultiplexers on-chip with the qubit devices advantageously allows reducing the number of input/output lines coupling the chip with qubit devices and the external electronics.
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公开(公告)号：US20190044066A1
公开(公告)日：2019-02-07
申请号：US15928220
申请日：2018-03-22
申请人： INTEL CORPORATION
发明人： Nicole K. Thomas , Marko Radosavljevic , Sansaptak Dasgupta , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke
CPC分类号： H01L49/006 , B82Y10/00 , B82Y20/00 , B82Y40/00 , G02B6/12004 , G02B2006/12078 , G02B2006/12142 , G06N10/00 , Y10S977/814 , Y10S977/933
摘要： Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.
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公开(公告)号：US20190044049A1
公开(公告)日：2019-02-07
申请号：US15900674
申请日：2018-02-20
申请人： Intel Corporation
发明人： Nicole K. Thomas , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke , Willy Rachmady
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.
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公开(公告)号：US20190044048A1
公开(公告)日：2019-02-07
申请号：US15891518
申请日：2018-02-08
申请人： Intel Corporation
发明人： Hubert C. George , Zachary R. Yoscovits , Nicole K. Thomas , Lester Lampert , James S. Clarke , Jeanette M. Roberts , Ravi Pillarisetty , David J. Michalak , Kanwaljit Singh , Roman Caudillo
IPC分类号： H01L39/14 , H01L39/22 , H01L29/12 , H01L29/15 , H01L29/423 , H01L29/40 , H01L39/24 , G06N99/00
CPC分类号： H01L39/146 , G06N10/00 , H01L23/445 , H01L23/46 , H01L23/49822 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L25/16 , H01L29/127 , H01L29/151 , H01L29/401 , H01L29/42316 , H01L39/228 , H01L39/24 , H01L2224/13101 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/014 , H01L2924/00014
摘要： Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.
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