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公开(公告)号:US11183564B2
公开(公告)日:2021-11-23
申请号:US16015087
申请日:2018-06-21
申请人: Intel Corporation
发明人: Nicole K. Thomas , Ravi Pillarisetty , Payam Amin , Roza Kotlyar , Patrick H. Keys , Hubert C. George , Kanwaljit Singh , James S. Clarke , David J. Michalak , Lester Lampert , Zachary R. Yoscovits , Roman Caudillo , Jeanette M. Roberts
IPC分类号: H01L29/12 , H01L29/66 , H01L29/76 , H01L29/423 , H01L29/165 , H01L27/18 , H01L21/8234 , H01L29/10 , G06N10/00 , H01L39/14 , H01L29/06 , B82Y10/00 , H01L29/82 , H01L29/40 , H01L21/321 , H01L21/02 , H01L29/778 , H01L29/43
摘要: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.
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公开(公告)号:US11063040B2
公开(公告)日:2021-07-13
申请号:US16340512
申请日:2016-12-24
申请人: Intel Corporation
发明人: James S. Clarke , Nicole K. Thomas , Zachary R. Yoscovits , Hubert C. George , Jeanette M. Roberts , Ravi Pillarisetty
IPC分类号: H01L27/088 , G06N10/00 , H01L21/8234 , H01L27/18 , H01L29/66 , H01L29/778 , B82Y10/00
摘要: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.
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公开(公告)号:US20200373351A1
公开(公告)日:2020-11-26
申请号:US16635193
申请日:2017-09-18
申请人: Intel Corporation
发明人: Jeanette M. Roberts , Wesley T. Harrison , Adel A. Elsherbini , Stefano Pellerano , Zachary R. Yoscovits , Lester Lampert , Ravi Pillarisetty , Roman Caudillo , Hubert C. George , Nicole K. Thomas , David J. Michalak , Kanwaljit Singh , James S. Clarke
摘要: Embodiments of the present disclosure propose qubit substrates, as well as methods of fabricating thereof and related device assemblies. In one aspect of the present disclosure, a qubit substrate includes a base substrate of a doped semiconductor material, and a layer of a substantially intrinsic semiconductor material over the base substrate. Engineering a qubit substrate in this manner allows improving coherence times of qubits provided thereon, while, at the same time, being sufficiently mechanically robust so that it can be efficiently used in large-scale manufacturing.
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公开(公告)号:US20190334020A1
公开(公告)日:2019-10-31
申请号:US16349955
申请日:2016-12-14
申请人: Intel Corporation
发明人: Payam Amin , Nicole K. Thomas , James S. Clarke , Jessica M. Torres , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Van H. Le , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , David J. Michalak
IPC分类号: H01L29/775 , H01L29/12 , H01L29/165 , H01L29/66 , H01L21/02 , G06N10/00
摘要: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.
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公开(公告)号:US20190273197A1
公开(公告)日:2019-09-05
申请号:US16347097
申请日:2016-12-27
申请人: Intel Corporation
发明人: Jeanette M. Roberts , Adel A. Elsherbini , Shawna Liff , Johanna M. Swan , Roman Caudillo , Zachary R. Yoscovits , Nicole K. Thomas , Ravi Pillarisetty , Hubert C. George , James S. Clarke
摘要: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.
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公开(公告)号:US20190206991A1
公开(公告)日:2019-07-04
申请号:US16314779
申请日:2016-08-12
申请人: Intel Corporation
发明人: Ravi Pillarisetty , Jeanette M. Roberts , David J. Michalak , Zachary R. Yoscovits , James S. Clarke
IPC分类号: H01L29/06 , H01L29/423 , H01L29/76 , H01L29/165 , H01L29/778 , H01L29/66
CPC分类号: H01L29/0673 , B82Y10/00 , H01L29/12 , H01L29/127 , H01L29/165 , H01L29/423 , H01L29/42376 , H01L29/66 , H01L29/66977 , H01L29/7613 , H01L29/7782 , H01L29/82
摘要: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of first gates disposed above the quantum well stack, wherein at least two of the first gates are spaced apart in a first dimension above the quantum well stack, at least two of the first gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and a second gate disposed above the quantum well stack, wherein the second gate extends between at least two of the first gates spaced apart in the first dimension, and the second gate extends between at least two of the first gates spaced apart in the second dimension.
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公开(公告)号:US20190044045A1
公开(公告)日:2019-02-07
申请号:US15924410
申请日:2018-03-19
申请人: Intel Corporation
发明人: Nicole K. Thomas , James S. Clarke , Jessica M. Torres , Lester Lampert , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , David J. Michalak
CPC分类号: H01L39/025 , B82Y10/00 , G06N10/00 , H01L29/127 , H01L29/423 , H01L29/66439 , H01L29/66977 , H01L29/66984 , H01L29/7613 , H01L39/045 , H01L39/223 , H01L39/249 , H01L39/2493 , H03K17/92
摘要: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.
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公开(公告)号:US20190043975A1
公开(公告)日:2019-02-07
申请号:US16017031
申请日:2018-06-25
申请人: Intel Corporation
发明人: Hubert C. George , David J. Michalak , Ravi Pillarisetty , Lester Lampert , James S. Clarke , Zachary R. Yoscovits , Nicole K. Thomas , Roman Caudillo , Kanwaljit Singh , Jeanette M. Roberts
IPC分类号: H01L29/778 , H01L29/12 , H01L29/06 , H01L29/66 , H01L21/8234 , H01L29/15 , H01L27/088 , H01L29/10 , G06N99/00
摘要: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.
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公开(公告)号:US20190043968A1
公开(公告)日:2019-02-07
申请号:US15924407
申请日:2018-03-19
申请人: Intel Corporation
发明人: Lester Lampert , James S. Clarke , Jeanette M. Roberts , Ravi Pillarisetty , David J. Michalak , Kanwaljit Singh , Roman Caudillo , Hubert C. George , Zachary R. Yoscovits , Nicole K. Thomas
摘要: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.
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公开(公告)号:US20190043951A1
公开(公告)日:2019-02-07
申请号:US16015087
申请日:2018-06-21
申请人: Intel Corporation
发明人: Nicole K. Thomas , Ravi Pillarisetty , Payam Amin , Roza Kotlyar , Patrick H. Keys , Hubert C. George , Kanwaljit Singh , James S. Clarke , David J. Michalak , Lester Lampert , Zachary R. Yoscovits , Roman Caudillo , Jeanette M. Roberts
IPC分类号: H01L29/12 , H01L29/10 , H01L29/423 , H01L29/165 , H01L21/02 , H01L29/66 , H01L29/778 , G06N99/00
摘要: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.
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