Invention Grant
- Patent Title: Gate arrangements in quantum dot devices
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Application No.: US15900655Application Date: 2018-02-20
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Publication No.: US10475912B2Publication Date: 2019-11-12
- Inventor: Nicole K. Thomas , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke , Willy Rachmady
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: H01L39/00
- IPC: H01L39/00 ; H01L29/778 ; H01L29/78 ; H01L29/51 ; H01L29/66 ; G06N10/00 ; H01L39/02 ; H01L29/82

Abstract:
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.
Public/Granted literature
- US20190043974A1 GATE ARRANGEMENTS IN QUANTUM DOT DEVICES Public/Granted day:2019-02-07
Information query
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