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公开(公告)号:US10790253B2
公开(公告)日:2020-09-29
申请号:US16576380
申请日:2019-09-19
IPC分类号: H01L23/00
摘要: A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core.
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公开(公告)号:US10553555B2
公开(公告)日:2020-02-04
申请号:US15686645
申请日:2017-08-25
IPC分类号: H01L21/30 , H01L23/00 , H01L23/498
摘要: A semiconductor structure which includes a first semiconductor substrate having a first plurality of copper connectors; a second semiconductor substrate having a second plurality of copper connectors; and a joining structure joining the first plurality of copper connectors to the second plurality of copper connectors, the joining structure including a copper intermetallic mesh having pores filled with silver. There is also a method for joining two semiconductor substrates.
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公开(公告)号:US10290599B2
公开(公告)日:2019-05-14
申请号:US15829492
申请日:2017-12-01
IPC分类号: H01L23/00
摘要: A method of fabricating a pillar-type connection includes forming a second conductive layer on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with a hollow core of the first conductive layer.
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公开(公告)号:US10068864B2
公开(公告)日:2018-09-04
申请号:US15453113
申请日:2017-03-08
IPC分类号: H01L23/48 , H01L23/00 , H01L21/56 , H01L25/065 , H01L25/00
摘要: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.
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公开(公告)号:US20180082968A1
公开(公告)日:2018-03-22
申请号:US15829506
申请日:2017-12-01
IPC分类号: H01L23/00
CPC分类号: H01L24/13 , H01L24/03 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/0401 , H01L2224/05 , H01L2224/05166 , H01L2224/05187 , H01L2224/05647 , H01L2224/10126 , H01L2224/11001 , H01L2224/11462 , H01L2224/1147 , H01L2224/13011 , H01L2224/13019 , H01L2224/13026 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/16238 , H01L2224/81141 , H01L2224/81143 , H01L2224/81815 , H01L2924/01029 , H01L2924/381 , H01L2924/00014 , H01L2924/04941 , H01L2924/0496 , H01L2924/01074 , H01L2924/01024 , H01L2924/00012 , H01L2924/014 , H01L2924/01027
摘要: A method of fabricating a pillar-type connection includes forming a first conductive layer. A second conductive layer is formed on the first conductive layer to define a conductive pillar that includes a top surface defining a recess aligned with a hollow core of the first conductive layer. A conductive via that terminates at a top surface of the first conductive layer is formed.
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公开(公告)号:US20170179068A1
公开(公告)日:2017-06-22
申请号:US14974165
申请日:2015-12-18
CPC分类号: H01L24/81 , B23K35/025 , B23K35/262 , B23K35/302 , B23K35/3033 , H01L21/4853 , H01L21/52 , H01L21/563 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05572 , H01L2224/05666 , H01L2224/1132 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13211 , H01L2224/13347 , H01L2224/13355 , H01L2224/13447 , H01L2224/13455 , H01L2224/13541 , H01L2224/13647 , H01L2224/13655 , H01L2224/16237 , H01L2224/16238 , H01L2224/16503 , H01L2224/16507 , H01L2224/17505 , H01L2224/73204 , H01L2224/81011 , H01L2224/81024 , H01L2224/8112 , H01L2224/81193 , H01L2224/81211 , H01L2224/8181 , H01L2224/81815 , H01L2224/8191 , H01L2224/81911 , H01L2924/0132 , H01L2924/01074 , H01L2924/00014 , H01L2924/014 , H01L2924/01029 , H01L2924/01028 , H01L2924/00012
摘要: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.
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公开(公告)号:US20170162536A1
公开(公告)日:2017-06-08
申请号:US15041381
申请日:2016-02-11
IPC分类号: H01L23/00 , H01L25/065 , H01L21/56 , H01L25/00
CPC分类号: H01L24/13 , H01L21/56 , H01L21/563 , H01L21/76838 , H01L21/7684 , H01L23/3171 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2224/03416 , H01L2224/0345 , H01L2224/03452 , H01L2224/03912 , H01L2224/0401 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05571 , H01L2224/05647 , H01L2224/05666 , H01L2224/05671 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11474 , H01L2224/11632 , H01L2224/13017 , H01L2224/13019 , H01L2224/13026 , H01L2224/13078 , H01L2224/13082 , H01L2224/131 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13184 , H01L2224/1601 , H01L2224/2919 , H01L2224/73204 , H01L2224/8112 , H01L2224/81193 , H01L2224/81203 , H01L2224/81345 , H01L2224/81365 , H01L2224/81385 , H01L2224/81801 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/2011 , H01L2924/3511 , H01L2924/00014 , H01L2924/00012 , H01L2924/01074 , H01L2924/01024 , H01L2924/01029 , H01L2924/069 , H01L2924/014
摘要: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.
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公开(公告)号:US20150325540A1
公开(公告)日:2015-11-12
申请号:US14788945
申请日:2015-07-01
发明人: Timothy H. Daubenspeck , Jeffrey P. Gambino , Ekta Misra , Christopher D. Muzzy , Wolfgang Sauter
CPC分类号: H01L24/81 , H01L23/3171 , H01L23/481 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/036 , H01L2224/03602 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05023 , H01L2224/05026 , H01L2224/0508 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05568 , H01L2224/0558 , H01L2224/05655 , H01L2224/1134 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13025 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81815 , H01L2924/014 , H01L2924/00014 , H01L2924/01027 , H01L2924/01026 , H01L2924/00012 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953
摘要: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.
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公开(公告)号:US09165831B2
公开(公告)日:2015-10-20
申请号:US13928676
申请日:2013-06-27
发明人: Timothy H. Daubenspeck , Jeffrey P. Gambino , Charles F. Musante , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号: H01L21/78 , H01L21/283
CPC分类号: H01L21/78 , H01L21/283
摘要: A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the wafer, filling the plurality of dicing channels with a fill material and removing a portion of the wafer from a back side of the wafer until the desired final thickness is achieved, where a portion of the fill material within the plurality of dicing channel is exposed. The method further including depositing a metal layer on the back side of the wafer; removing the fill material from within the plurality of dicing channels to expose the metal layer at a bottom of the plurality of dicing channels, and removing a portion of the metal layer located at the bottom of the plurality of dicing channels.
摘要翻译: 一种包括在晶片的前侧形成多个切割通道的方法; 多个切割通道包括至少大于晶片的期望最终厚度的深度,用填充材料填充多个切割通道,并从晶片的背面去除晶片的一部分,直到期望的最终厚度为 其中多个切割通道内的填充材料的一部分被暴露。 该方法还包括在晶片的背面沉积金属层; 从所述多个切割通道内移除所述填充材料以暴露所述多个切割通道的底部处的所述金属层,以及去除位于所述多个切割通道的底部的所述金属层的一部分。
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公开(公告)号:US09159696B2
公开(公告)日:2015-10-13
申请号:US14026158
申请日:2013-09-13
发明人: Timothy H. Daubenspeck , Jeffrey P. Gambino , Ekta Misra , Christopher D. Muzzy , Wolfgang Sauter
CPC分类号: H01L24/81 , H01L23/3171 , H01L23/481 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/036 , H01L2224/03602 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05023 , H01L2224/05026 , H01L2224/0508 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05568 , H01L2224/0558 , H01L2224/05655 , H01L2224/1134 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13025 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81815 , H01L2924/014 , H01L2924/00014 , H01L2924/01027 , H01L2924/01026 , H01L2924/00012 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953
摘要: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.
摘要翻译: 焊接凸块连接和制造焊料凸点连接的方法。 在电介质层上形成钝化层。 通孔开口从钝化层的顶表面延伸穿过钝化层到介电层中的金属线。 钝化层的顶表面上的掩模包括与通孔开口对准的掩模开口。 导电层选择性地形成在通路孔和掩模开口中。 导电层突出在钝化层的顶表面之上。 该方法还包括平坦化钝化层和导电层以限定与金属线耦合的通孔孔中的插塞。
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