Invention Publication
- Patent Title: SEMICONDUCTOR DEVICE ASSEMBLY INTERCONNECTION PILLARS AND ASSOCIATED METHODS
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Application No.: US17875778Application Date: 2022-07-28
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Publication No.: US20240038707A1Publication Date: 2024-02-01
- Inventor: Andrew M. Bayless , Cassie M. Bayless , Brandon P. Wirz
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.
Information query
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