公开(公告)号：US20170358545A1

公开(公告)日：2017-12-14

申请号：US15440621

申请日：2017-02-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JU-IL CHOI ,  HYOJU KIM ,  KWANGJIN MOON ,  SUJEONG PARK ,  JUBIN SEO ,  NAEIN LEE ,  HO-JIN LEE

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

公开(公告)号：US09589920B2

公开(公告)日：2017-03-07

申请号：US14836111

申请日：2015-08-26

申请人： Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

发明人： Dror Hurwitz ,  Alex Huang

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L21/78 ,  H01L21/027 ,  H01L21/683 ,  H01L23/495 ,  H01L23/14 ,  H01L21/56 ,  H01L23/13

CPC分类号： H01L24/16 ,  H01L21/0273 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/13 ,  H01L23/142 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49548 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/08 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/12105 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012

摘要： An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.

摘要翻译： 一种嵌入式管芯封装和制造方法，所述管芯封装包括在钝化层中具有I / O接触焊盘的管芯，其中所述管芯接触焊盘通过粘合/阻挡层耦合到特征层的第一侧，以及层 支柱从特征层的第二侧延伸，模具，特征层和柱状层被电介质材料包封，并且其中特征层包括在光学引导下通过光致抗蚀剂的激光曝光单独拉制的布线 成像系统，用于与管芯的I / O接触焊盘两者良好的对准，并随后沉积相对于封装边缘定位的柱。

公开(公告)号：US09275967B2

公开(公告)日：2016-03-01

申请号：US14148482

申请日：2014-01-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Min Liang ,  Jiun-Yi Wu

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/66

CPC分类号： H01L23/49838 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/17132 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81815 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/05042 ,  H01L2924/0533 ,  H01L2924/0534 ,  H01L2924/05342 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/05994 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2924/15787 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0268 ,  H05K1/113 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0353 ,  H01L2924/014 ,  H01L2924/00014

摘要： A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

摘要翻译： 提供了一个管芯和一个衬底。 芯片包括至少一个集成电路芯片，并且该基板包括至少部分延伸穿过其中的导电柱的第一和第二子集。 导电柱的第一子集中的每一个包括从衬底的表面突出的突出隆起焊盘，并且导电柱的第二子集各自部分地形成凹陷在衬底的表面内的迹线。 裸片经由多个导电凸块耦合到基板，每个导电凸块在突起凸块焊盘和模具中的一个之间延伸。

公开(公告)号：US08786165B2

公开(公告)日：2014-07-22

申请号：US11521828

申请日：2006-09-15

申请人： Andreas Alfred Hase

发明人： Andreas Alfred Hase

IPC分类号： H01L41/00 ,  H02N2/00 ,  H01L23/06

CPC分类号： H01L24/11 ,  B81C1/00333 ,  H01L23/04 ,  H01L23/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/11614 ,  H01L2224/291 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1532 ,  H01L2924/161 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/166 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A leadless package and method for manufacturing silicon based leadless QFN/SON compatible packages are described. In addition the package allows for hermetic sealing of devices while maintaining electrical and optical access. Micro-vias with feed-through metallization through a silicon structure facilitates a surface mount technology-compatible silicon package with bottom SMT pads and top surface device integration. Sloped edges on the SMT side enable solder filleting for post solder inspection. Hermetic seal can be attained for example using anodic bonding of a glass lid or using metal soldering. Metal soldering enables the use of solder bumps to provide electrical connections for the package to the lid with integrated device functionality used for sealing. Hermetically sealed silicon packages eliminates the need for an extra packaging layer required in plastic packages and provides a standard interface for enclosing one or more discrete devices.

摘要翻译： 描述了一种用于制造基于硅的无引脚QFN / SON兼容封装的无引线封装和方法。 此外，该封装允许在保持电和光学访问的同时对器件进行气密密封。 通过硅结构进行直通金属化的微通孔有利于具有底部SMT焊盘和顶部表面器件集成的表面贴装技术兼容的硅封装。 SMT侧边缘的边缘可以进行焊锡切割以进行焊后检测。 例如使用玻璃盖的阳极接合或使用金属焊接可以实现密封。 金属焊接使得可以使用焊料凸块为封装提供电连接，并具有用于密封的集成器件功能。 密封硅封装不需要塑料封装所需的额外封装层，并提供用于封装一个或多个分立器件的标准接口。

公开(公告)号：US20140159235A1

公开(公告)日：2014-06-12

申请号：US14073144

申请日：2013-11-06

申请人： FUJITSU LIMITED

发明人： Muneyuki Odaira

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11614 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/00

摘要： An electronic component includes an electrode portion and a solder portion formed on the electrode portion. In the electronic component, the electrode portion includes a first conductive portion and a second conductive portion each having different diffusion coefficient with respect to a component of the solder portion on a top surface of the electrode portion, and the solder portion is formed on the first conductive portion and the second conductive portion.

摘要翻译： 电子部件包括在电极部上形成的电极部和焊料部。 在电子部件中，电极部包括第一导电部和第二导电部，所述第一导电部和第二导电部相对于电极部的顶面上的焊料部的成分具有不同的扩散系数，焊料部形成在第一导电部 导电部分和第二导电部分。

公开(公告)号：US20130270697A1

公开(公告)日：2013-10-17

申请号：US13861073

申请日：2013-04-11

申请人： LAPIS SEMICONDUTOR CO., LTD.

发明人： OSAMU KOIKE

IPC分类号： H01L23/498 ,  H01L23/367

CPC分类号： H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3677 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/04042 ,  H01L2224/1146 ,  H01L2224/11614 ,  H01L2224/11616 ,  H01L2224/1162 ,  H01L2224/48463 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00

摘要： A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to any of the substrate and the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part to the top part to connect the bottom part and the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, the ring-like projection part being formed in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

摘要翻译： 具有柱状部件的装置包括基板; 布置在所述基板上的布线层; 以及设置在所述基板和所述布线层中的任一个上的柱状部件，所述柱状部件具有连接到所述基板和所述布线层中的任一个的底部，与所述底部相对的顶部， 面部从底部延伸到顶部，以连接底部和顶部; 其中每个所述柱状部件包括通过电镀形成的第一柱状部分，通过电镀形成在所述第一柱状部分上的第二柱状部分和形成在所述侧面部分上的环状突出部分 沿圆周方向向外延伸，所述环状突起部形成在比所述第一柱状部与所述第二柱状部之间的接合位置更高的位置。

公开(公告)号：US20120049346A1

公开(公告)日：2012-03-01

申请号：US12871565

申请日：2010-08-30

申请人： Cheng-Chung Lin ,  Chung-Shi Liu ,  Meng-Wei Chou ,  Kuo Cheng Lin ,  Wen-Hsiung Lu ,  Chien Ling Hwang ,  Ying-Jui Huang ,  De-Yuan Lu

发明人： Cheng-Chung Lin ,  Chung-Shi Liu ,  Meng-Wei Chou ,  Kuo Cheng Lin ,  Wen-Hsiung Lu ,  Chien Ling Hwang ,  Ying-Jui Huang ,  De-Yuan Lu

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/02052 ,  H01L21/32125 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/1084 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05573 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11614 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/1191 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0541 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/20102 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/207

摘要： Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

摘要翻译： 用于提供焊料柱凸块的装置和方法。 通过在集成电路的端子上通过导电材料的电镀形成导电材料的支柱，在集成电路的输入/输出端子上形成支柱凸点连接。 柱状凸块的基部具有比上部更大的宽度。 柱形凸起的基部的横截面可以形成梯形，矩形或倾斜的形状。 焊料可以形成在柱的顶表面上。 所得到的焊料柱凸起形成比现有技术更可靠的细间距封装焊接连接。

公开(公告)号：US20110233761A1

公开(公告)日：2011-09-29

申请号：US12730411

申请日：2010-03-24

申请人： Chien Ling Hwang ,  Yi-Wen Wu ,  Chun-Chieh Wang ,  Chung-Shi Liu

发明人： Chien Ling Hwang ,  Yi-Wen Wu ,  Chun-Chieh Wang ,  Chung-Shi Liu

IPC分类号： H01L23/50

CPC分类号： H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/023 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03901 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1182 ,  H01L2224/11827 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16238 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/01028 ,  H01L2924/01022 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/00

摘要： Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.

摘要翻译： 提供了用于Cu柱凸点技术的侧壁保护工艺，其中Cu柱凸起的侧壁上的保护结构由非金属材料层，例如电介质材料层，聚合物材料层或聚合物材料层中的至少一个形成 其组合。

公开(公告)号：US20080213996A1

公开(公告)日：2008-09-04

申请号：US11894627

申请日：2007-08-20

申请人： Valery M. Dubin ,  Sridhar Balakrishnan ,  Mark Bohr

发明人： Valery M. Dubin ,  Sridhar Balakrishnan ,  Mark Bohr

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L21/288 ,  H01L21/4853 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/29111 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

摘要翻译： 与模具包装相关的方法，技术和结构。 在一个示例性实施例中，管芯封装互连结构包括半导体衬底和与半导体衬底接触的第一导电层。 第一导电层可以包括基底层金属。 基底层金属可以包括Cu。 示例性实施方式还可以包括与第一导电层接触的扩散阻挡层和在扩散阻挡层顶部的润湿层。 凸起层可以驻留在润湿层的顶部，其中凸起层可以包括Sn，并且Sn可以被电镀。 扩散阻挡层可以是无电解的并且可以适于防止Cu和Sn扩散通过扩散阻挡层。 此外，扩散阻挡层可以进一步适于抑制凸块层中的晶须型形成。

公开(公告)号：US11694970B2

公开(公告)日：2023-07-04

申请号：US17207022

申请日：2021-03-19

申请人： NXP B.V.

发明人： Douglas Michael Reber ,  Rishi Bhooshan

IPC分类号： H01L23/552 ,  H01L21/78 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L23/552 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11462 ,  H01L2224/11614 ,  H01L2224/13147 ,  H01L2924/1306 ,  H01L2924/14253 ,  H01L2924/3025 ,  H01L2924/3512

摘要： Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.