公开(公告)号：US20240341042A1

公开(公告)日：2024-10-10

申请号：US18746837

申请日：2024-06-18

Applicant: Atotech Deutschland GmbH & Co. KG

Inventor： Bert REENTS ,  Akif ÖZKÖK ,  Soungsoo KIM ,  Horst BRÜGGMANN ,  Herwig Josef BERTHOLD ,  Marcin KLOBUS ,  Thomas SCHIWON ,  Marko MIRKOVIC

IPC: H05K3/42 ,  C25D3/38 ,  C25D5/02 ,  C25D5/18 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  H01L21/48 ,  H01L21/768 ,  H05K3/10 ,  H05K3/18 ,  H05K3/46

CPC classification number: H05K3/425 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  H01L21/4857 ,  H01L21/76877 ,  H05K3/108 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4623 ,  H05K3/181 ,  H05K2203/0353 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1492

Abstract: The present invention refers to a method of preparing a high density interconnect printed circuit board (HDI PCB) or IC substrates including through-holes and/or grate structures filled with copper, which comprises the steps of:



a) providing a multi-layer substrate;
b) forming a non-copper conductive layer or a copper layer on the cover layer and on an inner surface of the through-hole, respectively on an inner surface of the grate structure;
c) forming a patterned masking film;
d) electrodepositing copper;
e) removing the masking film; and
f) electrodepositing a copper filling.

公开(公告)号：US10020245B2

公开(公告)日：2018-07-10

申请号：US14150795

申请日：2014-01-09

Applicant: Infineon Technologies AG

Inventor： Henrik Ewe ,  Joachim Mahler ,  Anton Prueckl ,  Stefan Landau

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H05K1/05 ,  H05K3/46

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/05 ,  H05K1/185 ,  H05K1/188 ,  H05K3/4644 ,  H05K2201/09745 ,  H05K2201/09972 ,  H05K2203/0353 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.

公开(公告)号：US09572256B2

公开(公告)日：2017-02-14

申请号：US14633864

申请日：2015-02-27

Applicant: IBIDEN CO., LTD.

Inventor： Kazuhiro Yoshikawa ,  Takashi Kariya

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/11 ,  H01L23/00 ,  H05K3/28 ,  H05K3/40 ,  H05K1/14 ,  H05K3/46 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/09 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K1/144 ,  H05K3/28 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3478 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/042 ,  H05K2201/068 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/10977 ,  H05K2201/2072 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/0405 ,  H05K2203/0594 ,  H05K2203/0597 ,  H05K2203/1184 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A printed wiring board includes an uppermost insulating layer, first pads positioned to mount an IC chip on the insulating layer, second pads positioned to mount a second printed wiring board on the insulating layer, metal posts formed on the second pads, respectively, such that the metal posts mount the second board over the chip, and a solder resist layer formed on the uppermost insulating layer and having first and second openings such that the first openings exposes the first pads and that the second openings exposes the second pads, respectively. The metal posts are formed such that each of the metal posts has a diameter which is smaller than a diameter of each of the second opening portions, and the second opening portions are formed such that the diameter of each of the second opening portions is smaller than a diameter of each of the second pads.

Abstract translation: 印刷布线板包括最上层的绝缘层，位于绝缘层上的IC芯片安装的第一焊盘，位于绝缘层上的第二印刷电路板安装的第二焊盘，分别形成在第二焊盘上的金属柱，使得 金属柱将第二板安装在芯片上，以及形成在最上层绝缘层上并具有第一和第二开口的阻焊层，使得第一开口暴露第一焊盘，并且第二开口分别暴露第二焊盘。 金属柱形成为使得每个金属柱的直径小于每个第二开口部的直径，并且第二开口部形成为使得每个第二开口部的直径小于 每个第二垫的直径。

公开(公告)号：US09549465B2

公开(公告)日：2017-01-17

申请号：US14365897

申请日：2012-12-12

Applicant: LG INNOTEK CO., LTD.

Inventor： Chang Woo Yoo ,  Yeong Uk Seo ,  Byeong Ho Kim ,  Hyun Seok Seo ,  Sang Myung Lee ,  Ki Do Chun

IPC: H05K1/11 ,  H05K7/10 ,  H05K1/02 ,  H05K3/46 ,  H05K3/06

CPC classification number: H05K1/0298 ,  H05K3/06 ,  H05K3/465 ,  H05K2201/0376 ,  H05K2203/0353

Abstract: Provided are a printed circuit board and a method of manufacturing the same, the printed circuit board according to the present invention, the printed circuit board, including: an insulating substrate having a plurality of circuit pattern grooves formed on a surface thereof; and a plurality of circuit patterns formed by burying the circuit pattern grooves, wherein the circuit patterns protrude as much as a predetermined thickness from an upper surface of the insulating substrate.

Abstract translation: 提供一种印刷电路板及其制造方法，根据本发明的印刷电路板，印刷电路板包括：绝缘基板，其表面上形成有多个电路图案槽; 以及通过掩埋电路图案凹槽形成的多个电路图案，其中电路图案从绝缘基板的上表面突出多达预定厚度。

公开(公告)号：US09275967B2

公开(公告)日：2016-03-01

申请号：US14148482

申请日：2014-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Min Liang ,  Jiun-Yi Wu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/66

CPC classification number: H01L23/49838 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/17132 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81815 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/05042 ,  H01L2924/0533 ,  H01L2924/0534 ,  H01L2924/05342 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/05994 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2924/15787 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0268 ,  H05K1/113 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0353 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

Abstract translation: 提供了一个管芯和一个衬底。 芯片包括至少一个集成电路芯片，并且该基板包括至少部分延伸穿过其中的导电柱的第一和第二子集。 导电柱的第一子集中的每一个包括从衬底的表面突出的突出隆起焊盘，并且导电柱的第二子集各自部分地形成凹陷在衬底的表面内的迹线。 裸片经由多个导电凸块耦合到基板，每个导电凸块在突起凸块焊盘和模具中的一个之间延伸。

公开(公告)号：US20160050769A1

公开(公告)日：2016-02-18

申请号：US14778677

申请日：2014-03-25

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Nobuyuki YOSHIDA

IPC: H05K3/42 ,  C25D7/12 ,  C25D5/34 ,  C25D5/48 ,  H05K1/02 ,  C23C18/16 ,  H05K3/06 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  C25D3/38 ,  C25D5/10

CPC classification number: H05K3/421 ,  C23C18/1653 ,  C23C18/405 ,  C25D3/38 ,  C25D5/02 ,  C25D5/10 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  C25D7/123 ,  H05K1/0298 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/115 ,  H05K3/06 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  H05K2203/1423

Abstract: To provide a method for manufacturing a multilayer wiring substrate, in which an insulating layer and a metal foil provided thereon are integrally laminated on an inner layer material having a wiring formed thereon, in which a hole for via hole is formed in the metal foil and the insulating layer, and in which the hole for via hole is filled with an electrolytic filled plating layer after a base electroless plating layer is formed, the method being featured in that, after the base electroless plating layer is formed, first, an electrolysis filled plating layer is formed to the extent that the hole for via hole is not completely filled, and then, after the surface of the electrolytic filled plating layer is etched, the hole for via hole is completely filled by an electrolytic filled plating layer.

Abstract translation: 为了提供一种制造多层布线基板的方法，其中设置在其上的绝缘层和金属箔一体层压在其上形成有布线的内层材料上，其中在金属箔中形成有用于通孔的孔， 绝缘层，在形成基底化学镀层之后，通孔的孔填充有电解填充的镀层，其特征在于，在形成基底化学镀层之后，首先，填充电解液 形成电镀层的程度为通孔的孔未完全填充，然后在电解填充镀层的表面被蚀刻后，通孔的孔完全由电解填充镀层填充。

公开(公告)号：US08642894B2

公开(公告)日：2014-02-04

申请号：US12689353

申请日：2010-01-19

Applicant: Tomoyuki Abe ,  Norikazu Ozaki

Inventor： Tomoyuki Abe ,  Norikazu Ozaki

IPC: H05K1/09

CPC classification number: H05K1/167 ,  H05K3/108 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4641 ,  H05K2201/0323 ,  H05K2201/0355 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0597 ,  H05K2203/1184 ,  H05K2203/1476

Abstract: Provided is a circuit board including a resin base, and a resistance element formed above the resin base. The resistance element includes a resistance pattern including an electrode portion and an extending portion, and an electrode formed on the electrode portion of the resistance pattern and including a foot portion reduced in thickness toward the extending portion.

Abstract translation: 提供了一种电路板，包括树脂基底和形成在树脂基底上方的电阻元件。 电阻元件包括电阻图案，其包括电极部分和延伸部分，以及电极，形成在电阻图案的电极部分上，并且包括朝向延伸部分减小厚度的脚部分。

公开(公告)号：US08502082B2

公开(公告)日：2013-08-06

申请号：US11215206

申请日：2005-08-31

Applicant: Benson Chan ,  John M. Lauffer

Inventor： Benson Chan ,  John M. Lauffer

IPC: H05K1/03 ,  H05K1/09

CPC classification number: H05K3/4641 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K3/383 ,  H05K2201/0355 ,  H05K2203/0353

Abstract: A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.

Abstract translation: 其中三个导电层（例如，电镀铜箔）被结合（例如，层叠）到两个电介质层的电路化基板。 物理地结合到相应电介质层的每个箔表面是光滑的（例如优选通过化学处理），并且可以在其上包括薄的有机层。 导电层中的一个可以用作接地或电压（功率）面，而另外两个可以用作具有多条独立信号线作为其一部分的信号面。 还提供了利用这种电路化基板的电气组件和信息处理系统，以及制造基板的方法。

公开(公告)号：US20120216946A1

公开(公告)日：2012-08-30

申请号：US13467726

申请日：2012-05-09

Applicant: Takaharu HONDO

Inventor： Takaharu HONDO

IPC: H05K3/22 ,  B22D25/02 ,  B23K31/02 ,  B32B37/02

CPC classification number: H05K3/205 ,  H05K3/207 ,  H05K3/4647 ,  H05K2201/0376 ,  H05K2203/0353 ,  Y10T156/10

Abstract: A method of manufacturing a wiring substrate, includes: a step of preparing a first metal circuit layer, one face of the first metal circuit layer has thereon a first conductor circuit and a first interlayer connecting section having a different height from that of the first conductor circuit; and a step of forming a first insulating resin layer covering the one face of the first metal circuit layer so that a tip end of the first interlayer connecting section is exposed.

Abstract translation: 一种制造布线基板的方法，包括：制备第一金属电路层的步骤，第一金属电路层的一个面上具有第一导体电路和与第一导体的高度不同的第一中间连接部 电路 以及形成覆盖所述第一金属电路层的所述一面的第一绝缘树脂层以使得所述第一层间连接部的前端露出的步骤。

公开(公告)号：US08220149B2

公开(公告)日：2012-07-17

申请号：US12230101

申请日：2008-08-22

Applicant: Hee-Bum Shin ,  Jeong-Ho Moon ,  Jae-Hyun Eom ,  Jee-Soo Mok

Inventor： Hee-Bum Shin ,  Jeong-Ho Moon ,  Jae-Hyun Eom ,  Jee-Soo Mok

IPC: H01K3/10

CPC classification number: H05K3/107 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/0353 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The printed circuit board can include a first insulation layer, a second insulation layer stacked over the first insulation layer, a circuit pattern and a via land buried in the second insulation layer, and a via made of a conductive material penetrating the first insulation layer and integrated with the via land. The circuit pattern and via land can be buried in the insulation material, and the circuit pattern, via land, and via can be formed simultaneously as an integrated structure. Thus, the electrical reliability between the wiring pattern and the via can be increased, the heat-releasing effect of the via can be improved, and the procedure for forming the circuit patterns, via lands, and vias can be simplified, allowing greater productivity in manufacturing the substrate.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 印刷电路板可以包括第一绝缘层，堆叠在第一绝缘层上的第二绝缘层，埋在第二绝缘层中的电路图案和通孔焊盘，以及由穿透第一绝缘层的导电材料制成的通孔，以及 与通路地相结合。 电路图案和通孔焊盘可以埋在绝缘材料中，并且电路图案，通过焊盘和通孔可以作为一体结构同时形成。 因此，可以提高布线图案和通孔之间的电可靠性，可以提高通孔的散热效果，并且可以简化通过焊盘和通孔形成电路图案的步骤，从而提高生产率 制造基板。