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公开(公告)号：US11903138B2
公开(公告)日：2024-02-13
申请号：US17383084
申请日：2021-07-22
申请人： INTEL CORPORATION
发明人： Eric Li , Kemal Aygun , Kai Xiao , Gong Ouyang , Zhichao Zhang
CPC分类号： H05K3/0026 , H05K1/0228 , H05K3/027 , H05K3/4694 , H05K2201/09227 , H05K2201/09727 , H05K2203/107 , H05K2203/1476
摘要： Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.
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公开(公告)号：US11862518B2
公开(公告)日：2024-01-02
申请号：US16914900
申请日：2020-06-29
IPC分类号： H01L21/768 , H01L23/522 , H01L21/288 , H01L21/033 , C23C18/16 , H01L23/532 , C25D5/02 , C25D7/12 , C25D5/10 , H05K3/24 , H05K3/18 , H05K3/42 , H01L49/02 , H05K1/02
CPC分类号： H01L21/76885 , C23C18/1605 , C23C18/1651 , C25D5/022 , C25D5/10 , C25D7/123 , H01L21/0331 , H01L21/2885 , H01L21/76846 , H01L21/76852 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L28/10 , H05K3/184 , H05K3/244 , H05K3/422 , H05K1/0265 , H05K3/188 , H05K3/424 , H05K2201/0367 , H05K2201/0391 , H05K2201/096 , H05K2201/09563 , H05K2201/09845 , H05K2203/0716 , H05K2203/1407 , H05K2203/1423 , H05K2203/1476
摘要： The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.
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3.发明公开公开(公告)号：US20230380077A1
公开(公告)日：2023-11-23
申请号：US18198361
申请日：2023-05-17
发明人： Hiroshi MAKINO , Paul GARLAND
CPC分类号： H05K3/4664 , H05K1/0298 , H05K2203/1126 , H05K2203/1476
摘要： The examples set forth herein involve inkjet printing one or more layers on a multilayer ceramic base. In some examples, the multilayer ceramic base is fired in a first firing process before one or more inkjet printed layers are printed on the multilayer ceramic base to form a combination package comprising the multilayer ceramic base and the one or more inkjet printed layers. In further examples, the combination package is fired in a second firing process.
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公开(公告)号：US20190215950A1
公开(公告)日：2019-07-11
申请号：US16358360
申请日：2019-03-19
CPC分类号： H05K1/0206 , H05K1/0209 , H05K1/09 , H05K1/112 , H05K1/181 , H05K3/0026 , H05K3/0035 , H05K3/42 , H05K2201/09509 , H05K2201/096 , H05K2201/09781 , H05K2201/09827 , H05K2201/09854 , H05K2203/107 , H05K2203/1476
摘要： A component carrier includes a layer stack formed of an electrically insulating structure and an electrically conductive structure. Furthermore, a bore extends into the layer stack and has a first bore section with a first diameter (D1) and a connected second bore section with a second diameter (D2) differing from the first diameter (D1). A thermally conductive material fills substantially the entire bore. The bore is in particular formed by laser drilling.
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公开(公告)号：US20180315911A1
公开(公告)日：2018-11-01
申请号：US15769893
申请日：2016-10-24
发明人： Bojan Tesanovic , Peter Riel
IPC分类号： H01L33/62 , H01L31/02 , H01L33/54 , H01L31/0203 , H01L33/58 , H01L31/0232 , H01L31/18
CPC分类号： H05K3/425 , H05K3/0014 , H05K3/007 , H05K3/284 , H05K2201/09118 , H05K2201/09845 , H05K2201/10121 , H05K2203/0733 , H05K2203/1461 , H05K2203/1476
摘要： An electrical-contact assembly includes electrical contacts with first and second electrical-contact surfaces on opposing sides of the assembly. The electrical-contact assembly is manufactured by a structurable process (e.g., photo-structurable process) and by electroplating. The first and second electrical-contact surfaces can be positioned with respect to each other with an accuracy, for example, of at least 5 microns. Further, the thickness of the electrical-contact assembly can be at most 17 microns in some cases. The electrical-contact assembly can include integrated active optoelectronic elements, overmolds, optical elements and non-transparent walls.
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公开(公告)号：US10061447B2
公开(公告)日：2018-08-28
申请号：US14806557
申请日：2015-07-22
发明人： Jiuzhi Xue
CPC分类号： G06F3/044 , G06F2203/04102 , G06F2203/04103 , G06F2203/04112 , H05K1/0296 , H05K3/1241 , H05K3/125 , H05K2201/0108 , H05K2201/09681 , H05K2203/0126 , H05K2203/1131 , H05K2203/1476
摘要： A flexible conductive coating including: a first plurality of conductive traces extending in a first direction and a second plurality of conductive traces, each of the conductive traces including metal nanoparticles and ones of the second plurality of conductive traces being electrically coupled to ones of the first plurality of conductive traces, wherein each of the first plurality of conductive traces includes two substantially parallel long sides and two rounded short sides connecting the two long sides, and wherein more of the metal nanoparticles are at an outer edge of each of the conductive traces than are at an inner region bounded by the sides of each of the conductive traces.
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公开(公告)号：US20180132349A1
公开(公告)日：2018-05-10
申请号：US15864754
申请日：2018-01-08
发明人： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
CPC分类号： H05K3/42 , H05K1/0284 , H05K1/0296 , H05K1/112 , H05K3/007 , H05K3/4647 , H05K2201/0376 , H05K2203/0733 , H05K2203/1476 , Y10T29/49165
摘要： A manufacturing method of a double layer circuit board comprises forming at least one connecting pillar on a first circuit, wherein the at least one connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the at least one connecting pillar; drilling the substrate to expose a portion of the second end of the at least one connecting pillar, wherein the other portion of the second end of the at least one connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the at least one connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.
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公开(公告)号：US09947611B2
公开(公告)日：2018-04-17
申请号：US15010279
申请日：2016-01-29
发明人： Ping Mei , Brent S. Krusor , David K. Biegelsen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76898 , H05K3/4069 , H05K3/4623 , H05K3/4685 , H05K2201/09609 , H05K2201/0979 , H05K2203/1476 , H05K2203/1572
摘要： Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical conductors is incorporated as part of the two sided circuit board. An array of through holes extend through the first surface and the second surface, arranged in a pattern and are configured to provide a common electrical connection area, wherein the common electrical connection area is associated with a portion of a particular one of the plurality of electrical conductors.
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公开(公告)号：US09788415B2
公开(公告)日：2017-10-10
申请号：US15096680
申请日：2016-04-12
申请人： FUJITSU LIMITED
发明人： Megumi Tanaka , Daisuke Usui
CPC分类号： H05K1/0251 , H01R12/585 , H01R12/7082 , H01R12/737 , H05K1/115 , H05K1/142 , H05K3/0047 , H05K3/429 , H05K2201/09545 , H05K2201/096 , H05K2201/10189 , H05K2201/10303 , H05K2201/1059 , H05K2203/0207 , H05K2203/1476
摘要： A circuit board includes: a first surface and a second surface opposite to the first surface; a through hole extending between the first surface and the second surface; a conductor covering an inner wall surface of the through hole, a first end and a second end of the conductor being terminated inside the through hole; and a wire connected to the conductor, wherein a sum of a length from a contact portion where the conductor contacts a connector pin inserted in the through hole to the first end of the conductor, and a length from a wire connecting portion where the conductor is connected to the wire to the second end of the conductor is 0.5 mm or less.
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公开(公告)号：US09750141B2
公开(公告)日：2017-08-29
申请号：US15122922
申请日：2015-03-11
申请人： UTILIGHT LTD
发明人： Amir Noy
CPC分类号： H05K3/12 , B41M3/008 , B41M5/26 , C09D17/00 , H05K1/0265 , H05K1/0271 , H05K1/095 , H05K2201/09736 , H05K2203/107 , H05K2203/1476
摘要： Described are an apparatus and a method for printing a high aspect ratio and/or specific vertical geometry pattern. The apparatus operates in a multi-pass printing mode and includes one or more paste dispensing mechanism configured to dispense a high viscosity paste to form a pattern on a substrate. At least one paste dispensing mechanism is configured to dispense the paste to a segment of the pattern printed at an earlier pass. The paste is dispensed to the relevant segment of the pattern earlier printed before the paste printed at the earlier made pass is dry or what is termed “wet-on-wet” printing.
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