ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20240349426A1

    公开(公告)日:2024-10-17

    申请号:US18751913

    申请日:2024-06-24

    发明人: Atsushi SAKURAI

    IPC分类号: H05K1/11 H05K1/02 H05K3/42

    摘要: An electronic component that includes: a substrate; a first electrode layer on the substrate and including conductive fillers and a binder; an insulation layer on the first electrode layer, the insulation layer having a via hole that penetrates the insulation layer in a lamination direction of the substrate, the first electrode layer, and the insulation layer; a second electrode layer on the insulation layer; and a via conductor in the via hole, the via conductor electrically coupling the first electrode layer and the second electrode layer, wherein a portion of the first electrode layer overlapping with the via hole in a top view includes a coupling layer coupled to the via conductor, the coupling layer having a content rate of the binder lower than a content rate of the binder in a portion of the first electrode layer positioned outside the via hole in the top view.

    Wiring substrate and method for manufacturing wiring substrate

    公开(公告)号:US11792929B2

    公开(公告)日:2023-10-17

    申请号:US17588457

    申请日:2022-01-31

    申请人: IBIDEN CO., LTD.

    摘要: A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor penetrating through the second insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer such that the coating film is adhering the first conductor layer and the second insulating layer. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is in contact with the connection conductor and the wiring pattern is covered by the coating film, the conductor pad of the first conductor layer has a surface facing the second insulating layer and having a first surface roughness higher than a surface roughness of a surface of the wiring pattern, and the coating film has opening such that the opening is exposing the conductor pad entirely.

    WIRING SUBSTRATE AND PROCESS FOR PRODUCING IT

    公开(公告)号:US20190141833A1

    公开(公告)日:2019-05-09

    申请号:US16238586

    申请日:2019-01-03

    申请人: AGC Inc.

    摘要: To provide a wiring substrate having excellent transmission characteristics, of which initial failure of a plating layer formed on an inner wall surface of a hole is suppressed regardless of the type of the pre-treatment applied to the inner wall surface of the hole, and of which the plating layer has favorable heat resistance, and a process for producing it.A wiring substrate 10 comprising an electrical insulator layer 20, a first conductor layer 32 formed on a first surface of the electrical insulator layer 20, a second conductor layer 34 formed on a second surface of the electrical insulator layer 20, and a plating layer 42 provided on an inner wall surface of a hole 40 which opens from the first conductor layer 32 through the second conductor layer 34; wherein the electrical insulator layer 20 has a heat resistant resin layer 22 containing a heat resistant resin and a resin powder; the resin powder is formed from a resin material containing a melt-formable fluororesin having a functional group such as a carbonyl group-containing group; the content of the resin powder is from 5 to 70 mass % to the heat resistant resin layer 22; and the electrical insulator layer 20 has a dielectric constant of from 2.0 to 3.5.