公开(公告)号：US11997799B2

公开(公告)日：2024-05-28

申请号：US17565473

申请日：2021-12-30

申请人： SHENNAN CIRCUITS CO., LTD.

发明人： Changsheng Tang

IPC分类号： H05K3/40 ,  H05K1/11 ,  H05K3/18 ,  H05K3/26 ,  H05K3/42

CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K3/188 ,  H05K3/26 ,  H05K3/424

摘要： The present application provides a method for manufacturing a printed circuit board and a printed circuit board. The method for manufacturing a printed circuit board includes: providing a core board, wherein the core board includes an insulating baseplate, and a first surface and/or a second surface opposite to the first surface of the insulating baseplate is provided with a plurality of pads; and laminating a medium layer on a side of the insulating baseplate provided with the plurality of pads to form a laminated layer at least partially embedded among the plurality of pads.

公开(公告)号：US20230345642A1

公开(公告)日：2023-10-26

申请号：US18214391

申请日：2023-06-26

申请人： AVERATEK CORPORATION

发明人： Michael Riley Vinson ,  Shinichi Iketani

IPC分类号： H05K3/42 ,  H05K3/00 ,  C25D7/00

CPC分类号： H05K3/424 ,  H05K3/0023 ,  C25D7/00 ,  H05K3/425 ,  H05K3/0044 ,  H05K2203/0723

摘要： The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

公开(公告)号：US11746433B2

公开(公告)日：2023-09-05

申请号：US16674052

申请日：2019-11-05

申请人： MacDermid Enthone Inc.

发明人： Donald Desalvo ,  Ron Blake ,  Carmichael Gugliotti ,  William J. Decesare ,  Richard Bellemare

IPC分类号： C25D3/38 ,  H05K3/42 ,  H05K1/18 ,  H05K1/02 ,  C25D5/18 ,  H05K7/20 ,  C25D7/00 ,  C25D5/02

CPC分类号： C25D3/38 ,  C25D5/02 ,  C25D5/18 ,  C25D7/00 ,  H05K1/0206 ,  H05K1/181 ,  H05K3/423 ,  H05K3/424 ,  H05K7/20154 ,  H05K2203/0789 ,  H05K2203/1492

摘要： A method of copper electroplating in the manufacture of printed circuit boards. The method is used for filling through-holes and micro-vias with copper. The method includes the steps of: (1) preparing an electronic substrate to receive copper electroplating thereon; (2) forming at least one of one or more through-holes and/or one or more micro-vias in the electronic substrate; and (3) electroplating copper in the at one or more through-holes and/or one or more micro-vias by contacting the electronic substrate with an acid copper electroplating solution. The acid copper plating solution comprises a source of copper ions; sulfuric acid; a source of chloride ions; a brightener; a wetter; and a leveler. The acid copper electroplating solution plates the one or more through-holes and/or the one or more micro-vias until metallization is complete.

公开(公告)号：US20230223324A1

公开(公告)日：2023-07-13

申请号：US18151250

申请日：2023-01-06

申请人： Regents of the University of Minnesota

发明人： Bethanie J Stadler ,  Rhonda R. Franklin

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01R12/52 ,  H05K1/18 ,  H05K1/14 ,  H05K3/36 ,  H05K3/34 ,  H05K3/00 ,  H05K3/42

CPC分类号： H01L23/49827 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/81 ,  H01L21/486 ,  H01L24/13 ,  H01R12/52 ,  H05K1/181 ,  H05K1/145 ,  H05K3/368 ,  H05K3/3436 ,  H05K3/3494 ,  H05K3/0014 ,  H05K3/424 ,  H01L2224/16235 ,  H01L2224/81222 ,  H01L2224/81815 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13138 ,  H01L2224/13109 ,  H01L2924/01014 ,  H05K2201/10378 ,  H01L2224/81192 ,  H05K2203/0723

摘要： A device includes a porous substrate that include a plurality of pores and a plurality of nanodevices dispersed in at least a portion of the plurality of pores. Each of the plurality of nanodevices includes a magnetic nanowire and a solder nanoparticle. The magnetic nanowires are configured to generate heat in response to an alternating magnetic field. The solder nanoparticles are configured to receive a portion of the heat and reflow to connect to one or more devices or surfaces.

公开(公告)号：US20230147650A1

公开(公告)日：2023-05-11

申请号：US17984032

申请日：2022-11-09

申请人： TSE CO., LTD

发明人： Byeong Yong LEE ,  Eun Ha PARK ,  Weon Bin JANG ,  Gun Won SEO ,  Kum Sun PARK ,  Chung Hyeon KIM

IPC分类号： H05K3/42 ,  H05K3/26

CPC分类号： H05K3/424 ,  H05K3/429 ,  H05K3/26 ,  H05K2203/0502 ,  H05K2203/0415 ,  H05K2203/0723 ,  H05K2203/0588

摘要： A method for manufacturing a multi-layer circuit board including an extreme fine via according to an embodiment of the disclosure may include: providing a board having one surface on at least a part of which an upper conductive layer is formed and the other surface on at least a part of which a lower conductive layer is formed; forming a lower metal layer on the other surface of the board; forming a first resist layer on the one surface of the board through a photolithography process, and forming a first opening on the first resist layer; forming a metal pillar by plating the first opening by using an electrolytic plating method; removing the first resist layer; forming an insulating layer on a location from which the first resist layer is removed; and evenly polishing the metal pillar and the insulating layer.

公开(公告)号：US10064271B2

公开(公告)日：2018-08-28

申请号：US15108405

申请日：2014-05-21

申请人： ZTE CORPORATION

发明人： Bi Yi ,  Fengchao Ma ,  Yonghui Ren ,  Wang Xiong ,  Yingxin Wang

IPC分类号： H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC分类号： H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/10303 ,  H05K2203/0207 ,  H05K2203/16

摘要： The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.

公开(公告)号：US09988730B2

公开(公告)日：2018-06-05

申请号：US15127433

申请日：2015-03-12

申请人： Atotech Deutschland GmbH

发明人： Tadahiro Nishigawa ,  Jun Higuchi ,  Hitoshi Ishikawa

IPC分类号： C25D5/34 ,  C25D3/38 ,  H05K3/46 ,  H05K3/42 ,  H05K1/02

CPC分类号： C25D5/34 ,  C25D3/38 ,  C25D5/56 ,  H05K1/0296 ,  H05K3/424 ,  H05K3/427 ,  H05K3/467 ,  H05K2201/032 ,  H05K2201/0329 ,  H05K2203/0793 ,  H05K2203/0796

摘要： In a substrate like a printed circuit board comprising an insulator and a copper layer laminated on part of the insulator, said insulator outer surface and said copper layer outer surface are simultaneously subjected to a process (1) comprising treatment with an alkali metal hydroxide solution, a process (2) comprising treatment with an alkaline aqueous solution containing an aliphatic amine, a process (3) comprising treatment with an alkaline aqueous solution having a permanganate concentration of 0.3 to 3.5 wt % and a pH of 8 to 11, a process (4) comprising treatment with an acidic microemulsion aqueous solution containing a thiophene compound and an alkali metal salt of polystyrenesulphonic acid, and a process (5) comprising copper electroplating, which are implemented sequentially.

公开(公告)号：US09872394B2

公开(公告)日：2018-01-16

申请号：US15090656

申请日：2016-04-05

申请人： International Business Machines Corporation

发明人： Steven A. Cordes ,  Bing Dang ,  Sung K. Kang ,  Yu Luo ,  Peter J. Sorce

IPC分类号： B05D5/12 ,  H05K3/00 ,  C25D5/02 ,  C25D7/00 ,  H05K3/42 ,  C23C18/16 ,  H05K3/38

CPC分类号： H05K3/0094 ,  C23C18/1603 ,  C23C18/1646 ,  C23C18/1653 ,  C23C18/1689 ,  C25D5/02 ,  C25D7/00 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/5384 ,  H05K3/388 ,  H05K3/424 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/308

摘要： A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.

公开(公告)号：US09831103B2

公开(公告)日：2017-11-28

申请号：US14995207

申请日：2016-01-14

申请人： Unimicron Technology Corp.

发明人： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

IPC分类号： H01L21/48 ,  C25D7/12 ,  C25D5/48 ,  C25D5/34 ,  C25D5/02 ,  H05K1/11 ,  H05K3/46 ,  C25D1/00 ,  H05K3/10 ,  H05K3/42

CPC分类号： H01L21/4857 ,  C25D1/003 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/113 ,  H05K3/10 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

摘要： A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

公开(公告)号：US09763327B2

公开(公告)日：2017-09-12

申请号：US14834180

申请日：2015-08-24

申请人： Multek Technologies Ltd.

发明人： Kwan Pen ,  Pui Yin Yu

IPC分类号： H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18

CPC分类号： H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

摘要： A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.