公开(公告)号：US12058818B2

公开(公告)日：2024-08-06

申请号：US17815575

申请日：2022-07-28

Applicant: IBIDEN CO., LTD.

Inventor： Satoru Kawai

IPC: C25D5/34 ,  C25D3/38 ,  C25D5/02 ,  C25D5/48 ,  H05K3/06 ,  H05K3/10 ,  H05K3/26 ,  H05K3/42

CPC classification number: H05K3/423 ,  C25D3/38 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  H05K3/061 ,  H05K3/108 ,  H05K3/26 ,  H05K3/427 ,  H05K2203/143 ,  H05K2203/1461

Abstract: A method for manufacturing a printed wiring board includes forming through holes in a double-sided copper-clad laminated plate such that a high-density region of the through holes and a low-density region of the through holes are formed, forming an electrolytic plating film on a copper foil of the plate in the high-density and low-density regions, forming a masking resist to mask the plating film in the high-density region, etching the plating film in the low-density region exposed from the resist such that the plating film in the low-density region is thinned, peeling off the resist from the plating film in the high-density region, and forming a conductor circuit including the copper foil and the plating film in the high-density and low-density regions. The forming of the plating film on the copper foil of the plate includes forming the plating film in the through holes in the high-density and low-density regions.

公开(公告)号：US20240196533A1

公开(公告)日：2024-06-13

申请号：US18208748

申请日：2023-06-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Youn Gyu Han ,  Jin Uk Lee ,  Jin Oh Park ,  Yong Duk Lee

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/32

CPC classification number: H05K1/115 ,  H05K1/03 ,  H05K1/111 ,  H05K3/323 ,  H05K2203/1461

Abstract: A printed circuit board includes a first insulating layer; a connection via penetrating through at least a portion of the first insulating layer and having an upper surface exposed to an upper surface of the first insulating layer; a cavity penetrating through at least a portion of the first insulating layer and having the upper surface of the first insulating layer as a bottom surface of the cavity; a bridge disposed in the cavity and having a first bridge pad disposed on a lower side of the bridge; and a bonding layer including conductive particles connected to the connection via and the first bridge pad.

公开(公告)号：US20170150592A1

公开(公告)日：2017-05-25

申请号：US15423584

申请日：2017-02-03

Applicant: MPI corporation

Inventor： WEI-CHENG KU ,  JUN-LIANG LAI ,  CHIH-HAO HO

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/18 ,  H05K3/421 ,  H05K3/426 ,  H05K3/429 ,  H05K2201/041 ,  H05K2201/09545 ,  H05K2203/0369 ,  H05K2203/1461

Abstract: A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate is provided with two first pads, two second pads, and two first sub-circuits. The first pads and the second pads are electrically connected to the first sub-circuits. The second substrate has a top surface, a bottom surface, a lateral edge, and two openings. The bottom surface of the second substrate is attached to the top surface of the first substrate. The openings extend from the top surface to the bottom surface of the second substrate. The first pads of the first substrate are in the opening of the second substrate; the second pads of the first substrate are not covered by the second substrate. The second substrate is further provided with a pad on the top surface and a second sub-circuit electrically connected to the pad of the second substrate.

公开(公告)号：US09392697B2

公开(公告)日：2016-07-12

申请号：US14327713

申请日：2014-07-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jin O Yoo

IPC: H05K1/11 ,  H05K1/18 ,  H01L25/00

CPC classification number: H05K1/185 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/81 ,  H01L24/96 ,  H01L25/00 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13186 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2924/01018 ,  H01L2924/19105 ,  H05K1/0296 ,  H05K1/11 ,  H05K3/3473 ,  H05K2203/1461

Abstract: A method of manufacturing a package may include forming a package module by disposing a plurality of components on an insulating plate filled with a viscous insulating liquid and curing the viscous insulating liquid, exposing at least portions of terminals of the plurality of components by polishing the insulating plate to have a predetermined thickness and then etching at least one portion of the insulating plate, forming a conductive stud on the at least exposed portions of the terminals and cutting the package module into predetermined unit packages, and examining reliability of a printed circuit board and bonding the unit package to the printed circuit board having confirmed reliability using the conductive stud.

Abstract translation: 制造封装的方法可以包括通过在填充有粘性绝缘液体的绝缘板上设置多个部件并固化粘性绝缘液体来形成封装模块，通过抛光绝缘材料来暴露多个部件的端部的至少一部分 板以具有预定厚度，然后蚀刻绝缘板的至少一部分，在端子的至少暴露部分上形成导电柱，并将封装模块切割成预定单元封装，并且检查印刷电路板的可靠性和 使用导电柱将单元封装结合到具有确认可靠性的印刷电路板。

公开(公告)号：US20160165721A1

公开(公告)日：2016-06-09

申请号：US14897200

申请日：2014-04-11

Applicant: AMOGREENTECH CO., LTD.

Inventor： O-Chung Kwon ,  Jeong-Sang Yu ,  Jae-Sic Kim ,  Yong-Il Kim ,  Hyun-Soo Jang

IPC: H05K1/03 ,  H05K3/46 ,  H05K3/40 ,  H05K3/12 ,  H05K3/28

CPC classification number: H05K3/4664 ,  H05K3/0014 ,  H05K3/007 ,  H05K3/1208 ,  H05K3/1216 ,  H05K3/1283 ,  H05K3/28 ,  H05K3/285 ,  H05K3/381 ,  H05K3/4069 ,  H05K2203/097 ,  H05K2203/1194 ,  H05K2203/1461 ,  H05K2203/1563 ,  H05K2203/1572

Abstract: A method for manufacturing a flexible printed circuit board includes preliminarily thermally deforming s substrate through heating, forming a circuit pattern with a conductive paste on the preliminarily thermally deformed substrate, and firing the circuit pattern. A flexible printed circuit board includes a substrate, and a circuit pattern formed by firing a conductive paste on a first surface of the substrate. The substrate is preliminarily thermally deformed and, thus, a shrinkage variation thereof before and after firing the conductive paste is zero. Dimensional stability when firing the circuit pattern printed with the conductive paste can be ensured, deterioration of adhesion between the circuit pattern and the substrate attributable to film deformation upon firing can be prevented, and stable adhesion of the circuit pattern can be maintained even after firing.

Abstract translation: 柔性印刷电路板的制造方法包括通过加热预先使基板热变形，在预热变形的基板上形成具有导电浆料的电路图案，并且对该电路图案进行点火。 柔性印刷电路板包括基板和通过在基板的第一表面上焙烧导电浆料形成的电路图案。 基板预热变形，因此，在导电浆料烧成前后的收缩变化为零。 可以确保烧制印有导电膏的电路图形时的尺寸稳定性，可以防止由于烧成时的膜变形引起的电路图案与基板之间的粘合性的劣化，即使在烧成后也能够保持电路图案的稳定的粘合。

公开(公告)号：US20160050794A1

公开(公告)日：2016-02-18

申请号：US14779916

申请日：2014-03-26

Applicant: INNOGRATION (SUZHOU) CO., LTD

Inventor： Chu Ming Shih ,  Gordon C. Ma

IPC: H05K7/20 ,  H05K3/00 ,  H05K3/30 ,  H05K7/02

CPC classification number: H05K7/20509 ,  H01L23/3677 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/19107 ,  H05K1/0204 ,  H05K3/0044 ,  H05K3/301 ,  H05K7/02 ,  H05K2201/0347 ,  H05K2201/10416 ,  H05K2203/1461

Abstract: An electronic component mounting structure, manufacturing method and an electronic component product are provided. The electronic component mounting structure comprises a printed circuit board, a metal flange, and a plurality of electronic components provided on the metal flange; a groove is provided on the printed circuit board, a metal layer is coated on a wall of the groove, the metal flange is restricted to the metal layer on the wall and is fixed in the groove, the one or more electronic components are connected to each other through a plurality of wires based on a circuit requirement, an input electrode and an output electrode are provided on the printed circuit board in a portion adjacent to the metal flange, and the input electrode and the output electrode are connected to the one or more electronic components mounted on the metal flange through wires respectively.

Abstract translation: 提供电子部件安装结构，制造方法和电子部件产品。 电子部件安装结构包括印刷电路板，金属凸缘和设置在金属凸缘上的多个电子部件; 在印刷电路板上设置有凹槽，金属层涂覆在凹槽的壁上，金属凸缘限于壁上的金属层并固定在凹槽中，一个或多个电子元件连接到 通过基于电路要求的多条导线，输入电极和输出电极设置在与金属凸缘相邻的部分的印刷电路板上，并且输入电极和输出电极连接到一个或 更多的电子元件分别安装在金属法兰上。

公开(公告)号：US20150327369A1

公开(公告)日：2015-11-12

申请号：US14760982

申请日：2013-01-18

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Yasuaki Seki ,  Tomoyuki Nagata ,  Mitsuaki Toda

IPC: H05K1/18 ,  H05K3/00 ,  H05K3/46 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/186 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/0206 ,  H05K1/0222 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09827 ,  H05K2201/10 ,  H05K2203/063 ,  H05K2203/1461 ,  Y10T156/10

Abstract: A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).

Abstract translation: 一种器件嵌入式衬底（20），包括：绝缘层（12），包括绝缘树脂材料; 嵌入所述绝缘层（12）中的电气或电子设备（4）; 用作包括在所述装置（4）中的电极的端子（15）; 形成在所述绝缘层（12）的表面上的导体图案（18）; 以及用于将导体图案（18）和端子（15）彼此电连接的导电通孔（21）。 导电通孔（21）由大直径的大直径部分（21a）和直径小于大直径部分（21a）直径的小直径部分（21b）构成，以便顺序起动 从导体图案（18）朝向端子（15）。 在大直径部分（21a）和小直径部分（21b）之间形成有阶梯部分（17）。 大直径部分21a形成为穿透设置在绝缘层12中的片状玻璃布11。

公开(公告)号：US09117697B2

公开(公告)日：2015-08-25

申请号：US14303371

申请日：2014-06-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che Lee ,  Yuan-Chang Su ,  Wen-Chi Cheng ,  Guo-Cheng Liao ,  Yi-Chuan Ding

IPC: H01L23/52 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Abstract translation: 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。

公开(公告)号：US20150208513A1

公开(公告)日：2015-07-23

申请号：US14593351

申请日：2015-01-09

Applicant: Panasonic Corporation

Inventor： KOICHI HIRANO

IPC: H05K3/00 ,  H05K3/12

CPC classification number: H05K3/4664 ,  B05D1/28 ,  B05D1/36 ,  B05D5/12 ,  B05D7/50 ,  B41F7/02 ,  H05K3/1275 ,  H05K2203/0108 ,  H05K2203/0143 ,  H05K2203/0537 ,  H05K2203/1461

Abstract: A manufacturing method for an electronic device according to the present disclosure includes (i) forming an insulating film on a surface of a cylinder, (ii) forming the insulating film having a via hole on the surface of the cylinder by pressing a relief member against the insulating film to remove a portion of the insulating film facing a protrusion of the relief member, and (iii) providing a precursor of an insulating layer having the via hole filled with conductive ink on a wiring substrate, wherein the via hole faces a wiring of the wiring substrate.

Abstract translation: 根据本公开的电子设备的制造方法包括（i）在圆筒的表面上形成绝缘膜，（ii）通过将浮雕元件按压在气缸表面上而形成具有通孔的绝缘膜 所述绝缘膜用于去除所述绝缘膜的面对所述浮雕构件的突起的部分，以及（iii）在布线基板上提供具有填充有导电油墨的通孔的绝缘层的前体，其中所述通孔面向布线 的布线基板。

公开(公告)号：US08991043B2

公开(公告)日：2015-03-31

申请号：US13553787

申请日：2012-07-19

Applicant: Chao-Min Wang

Inventor： Chao-Min Wang

IPC: H01K3/10 ,  H05K3/24 ,  H05K3/46 ,  H05K3/10

CPC classification number: H05K3/244 ,  H05K3/108 ,  H05K3/4652 ,  H05K2203/0361 ,  H05K2203/0574 ,  H05K2203/1461 ,  H05K2203/1572 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.

Abstract translation: 电路板结构包括核心电路结构，第一和第二电介质层，第一和第二导电盲孔结构，第三和第四图案化电路层以及第一和第二表面钝化层。 第一和第二介电层分别具有暴露核心电路结构的第一和第二图案化电路层的部分的至少一个第一和第二盲孔。 第一和第二导电盲通孔结构分别设置在第一和第二盲孔中。 第三和第四图案化电路层分别通过第一和第二导电盲孔结构电连接到第一和第二图案化电路层。 第一和第二表面钝化层分别暴露第三和第四图案化电路层的部分。