公开(公告)号：US09899342B2

公开(公告)日：2018-02-20

申请号：US15164888

申请日：2016-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Tzu-Yun Huang

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/11015 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/014

Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.

公开(公告)号：US09646944B2

公开(公告)日：2017-05-09

申请号：US15161346

申请日：2016-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Jung Yang ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/565 ,  H01L23/3192 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05541 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/11015 ,  H01L2224/1134 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14131 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

公开(公告)号：US20170025371A1

公开(公告)日：2017-01-26

申请号：US15194160

申请日：2016-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/768 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02255 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0382 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/11015 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/05994 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformity deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bum stop structure is also provided.

Abstract translation: 提供一种半导体器件的制造方法。 在该方法中，在金属化层中形成导电焊盘和金属突起图案。 钝化层被共形沉积在金属化之上，并且保护层在钝化层上沉积。 此外，钝化后互连结构（PPI）保形地形成在保护层上，并且PPI结构包括着陆焊盘区域，在着陆焊盘区域的至少一部分上的突出图案以及电连接到 导电垫。 然后将焊料凸块放置在与PPI结构的突出图案接触的着陆焊盘区域上。 还提供了具有烧结停止结构的半导体器件。

公开(公告)号：US09368417B2

公开(公告)日：2016-06-14

申请号：US14846614

申请日：2015-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Ying-Ju Chen

IPC: H01L21/66 ,  H01L23/482 ,  H01L23/00

CPC classification number: H01L22/34 ,  H01L22/30 ,  H01L22/32 ,  H01L23/4824 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/06505 ,  H01L2224/11015 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/014

Abstract: A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

公开(公告)号：US09362243B2

公开(公告)日：2016-06-07

申请号：US14283716

申请日：2014-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tsung-Yuan Yu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0213 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/11 ,  H01L2224/11015 ,  H01L2224/11334 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/014

Abstract: In some embodiments in accordance with the present disclosure, a semiconductor device having a semiconductor substrate is provided. A metal structure is disposed over the semiconductor substrate, and a post-passivation interconnect (PPI) is disposed over the metal structure. In addition, the upper surface of the PPI is configured to receive a bump thereon. In certain embodiments, the upper surface of the PPI for receiving the bump is substantially flat. A positioning member is formed over the PPI and configured to accommodate the bump. In some embodiments, the positioning member is configured to limit bump movement after the bump is disposed over the PPI so as to retain the bump at a predetermined position.

Abstract translation: 在根据本公开的一些实施例中，提供了具有半导体衬底的半导体器件。 金属结构设置在半导体衬底上，并且钝化后互连（PPI）设置在金属结构上。 此外，PPI的上表面被配置为在其上接收凸块。 在某些实施例中，用于接收凸块的PPI的上表面基本上是平的。 定位构件形成在PPI上并被构造成容纳凸起。 在一些实施例中，定位构件构造成在凸起布置在PPI上之后限制凸块移动，以便将凸块保持在预定位置。

公开(公告)号：US20150214170A1

公开(公告)日：2015-07-30

申请号：US14166531

申请日：2014-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L24/13 ,  H01L21/768 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02255 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0382 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/11015 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/05994 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided.

Abstract translation: 提供一种半导体器件的制造方法。 在该方法中，在金属化层中形成导电焊盘和金属突起图案。 钝化层在金属化之上共形沉积，保护层共形沉积在钝化层上。 此外，钝化后互连结构（PPI）保形地形成在保护层上，并且PPI结构包括着陆焊盘区域，在着陆焊盘区域的至少一部分上的突出图案以及电连接到 导电垫。 然后将焊料凸块放置在与PPI结构的突出图案接触的着陆焊盘区域上。 还提供了具有烧结停止结构的半导体器件。

公开(公告)号：US09048149B2

公开(公告)日：2015-06-02

申请号：US13940626

申请日：2013-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Yu-Chia Lai ,  Hsien-Ming Tu ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Chang-Pin Huang ,  Ching-Jung Yang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/10125 ,  H01L2224/11015 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

Abstract translation: 封装半导体器件包括半导体衬底，金属焊盘，金属基底，聚合物绝缘层，含铜结构和导电凸块。 金属焊盘和金属基底设置在半导体衬底上。 聚合物绝缘层覆盖金属基底和半导体基底。 含铜结构设置在聚合物绝缘层之上，并且包括支撑结构和钝化后互连（PPI）线。 支撑结构与金属基座对准。 PPI线部分地位于支撑结构内，并且通过支撑结构的开口延伸出，其中支撑结构的顶部升高到高于PPI线的顶部。 导电凸块由支撑结构保持。

公开(公告)号：US20150001704A1

公开(公告)日：2015-01-01

申请号：US13927972

申请日：2013-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chun-Lin LU ,  Kai-Chiang WU ,  Ming-Kai LIU ,  Yen-Ping WANG ,  Shih-Wei LIANG ,  Ching-Feng YANG ,  Chia-Chun MIAO ,  Hung-Jen LIN

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0554 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/11015 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81148 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract translation: 提供了用于形成封装结构的机构的实施例。 封装结构包括半导体管芯和衬底。 封装结构包括柱状凸起和与半导体管芯和衬底结合的细长焊料凸块。 细长焊料凸块的高度基本上等于柱形凸块的高度。 细长的焊料凸块在通过细长焊料凸块的侧壁表面的上端的第一水平面处具有第一宽度，并且在通过侧壁表面的中点的第二水平面处具有第二宽度。 第二宽度与第一宽度的比率在约0.5至约1.1的范围内。

公开(公告)号：US08896112B2

公开(公告)日：2014-11-25

申请号：US13838602

申请日：2013-03-15

Applicant: Oracle International Corporation

Inventor： Hiren D. Thacker ,  Ashok V. Krishnamoorthy ,  John E. Cunningham ,  Chaoqi Zhang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/14 ,  B23K3/0623 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/296 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/74 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05686 ,  H01L2224/11005 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13686 ,  H01L2224/17517 ,  H01L2224/742 ,  H01L2224/81002 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/05432 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2224/05552

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.

Abstract translation: 描述了多芯片模块（MCM）。 该MCM包括至少两个基板，其通过在基板的相对表面上的正和负特征机械耦合和对准。 这些积极和消极的特征可以彼此交配和自锁。 可以使用负特征中的亲水层，在至少一个基板上将负面特征自身填充到负极特征中。 该亲水层可以与围绕至少一个基底的顶表面上的负特征的疏水层结合使用。

公开(公告)号：US20070287225A1

公开(公告)日：2007-12-13

申请号：US11757724

申请日：2007-06-04

Applicant: Horst Theuss

Inventor： Horst Theuss

IPC: H01L21/00 ,  H01L21/44

CPC classification number: H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/10135 ,  H01L2224/11015 ,  H01L2224/11464 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/83194 ,  H01L2224/83907 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method of manufacturing an integrated circuit including a first isolated chip electrically and mechanically connected via wafer bonding to a second isolated chip, wherein the active faces of the chips face one another, includes: forming metallic contact zones on active faces of first and second wafers, positioning and fixing the wafers one above another at a predetermined distance such that the active faces of the wafers face one another and the contact zones are aligned, placing the fixed wafers in a bath for electroless metal deposition onto the contact zones; and removing the fixed wafers in the event that the metal layers growing on the aligned contact zones of the first and second wafers have grown together.

Abstract translation: 一种制造集成电路的方法，该集成电路包括通过晶片接合电和机械地连接到第二隔离芯片的第一隔离芯片，其中所述芯片的有源面彼此面对，包括：在第一和第二晶片的有效面上形成金属接触区 将晶片定位并固定在预定距离上，使得晶片的有效面彼此面对并且接触区域对准，将固定的晶片放置在用于无电金属沉积的浴中到接触区上; 并且在第一和第二晶片的对齐的接触区上生长的金属层已经一起生长的情况下去除固定晶片。