公开(公告)号：US20150270304A1

公开(公告)日：2015-09-24

申请号：US14734240

申请日：2015-06-09

申请人： OLYMPUS CORPORATION

发明人： Haruhisa Saito

IPC分类号： H01L27/146 ,  H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L27/14634 ,  H01L21/48 ,  H01L21/50 ,  H01L21/78 ,  H01L23/48 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/08112 ,  H01L2224/08135 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/1148 ,  H01L2224/1184 ,  H01L2224/13013 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/1411 ,  H01L2224/16057 ,  H01L2224/16106 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/8012 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device manufacturing method includes a wafer stack manufacturing process and a dicing process. The wafer stack manufacturing process includes: a first wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing electrodes electrically connected to the wirings in the first holes to form a first wafer; a second wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and a wafer bonding process.

摘要翻译： 半导体器件制造方法包括晶片堆叠制造工艺和切割工艺。 晶片堆栈制造工艺包括：制造树脂膜覆盖电路并被加热到高于树脂膜的玻璃化转变点的温度的第一晶片制造工艺，制造从树脂膜的表面延伸到第一孔的布线 并且提供与第一孔中的布线电连接以形成第一晶片的电极; 制造树脂膜覆盖电路并被加热到低于树脂膜的玻璃化转变点的温度的第二晶片制造工艺，制造从树脂膜的表面延伸到电路的布线的第二孔，并且将电极提供电 连接到第二孔中的布线以形成第二晶片; 和晶圆接合工艺。

公开(公告)号：US09087816B2

公开(公告)日：2015-07-21

申请号：US14190366

申请日：2014-02-26

申请人： Renesas Electronics Corporation

发明人： Soshi Kuroda ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L24/46 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512

摘要： To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

摘要翻译： 为了实现半导体器件的成本降低，在公共板（布线板）中，多个接合引线各自朝向基板的中心延伸，并且作为支撑最小芯片的芯片接合区域的阻焊膜为 涂有芯片接合材料。 由此，即使安装作为大芯片的第一半导体芯片，也可以在不使芯片接合材料覆盖接合引线的情况下进行引线接合。 因此，可以降低开发成本以降低半导体器件（LGA）的成本。

公开(公告)号：US20150123129A1

公开(公告)日：2015-05-07

申请号：US14072141

申请日：2013-11-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Chuan Teng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Li-Min Hung ,  Yao-Te Huang ,  Chin-Yi Cho

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L24/06 ,  B81B2207/012 ,  B81C99/0045 ,  B81C99/005 ,  H01L22/32 ,  H01L23/10 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/0605 ,  H01L2224/32145 ,  H01L2224/83194 ,  H01L2924/01322 ,  H01L2924/16235 ,  H01L2924/00

摘要： In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

摘要翻译： 在用于MEMS器件的晶片级芯片级封装技术中，首先在CMOS衬底的两个CMOS器件之间的刻划线区域上蚀刻深沟槽。 在将CMOS衬底与MEMS衬底结合之后，通过薄层化工艺来打开深沟槽，使得在衬底不是（部分单片化）的情况下将CMOS衬底分离。 MEMS基板上的电测试板被暴露，保护材料可以通过粘结层周围的深沟槽填充。 在填充保护材料之后，将晶片切割成形成封装的独立芯片，保护结合层外部的环境。

公开(公告)号：US20140203444A1

公开(公告)日：2014-07-24

申请号：US14225923

申请日：2014-03-26

申请人： FUJITSU LIMITED

发明人： KOZO SHIMIZU ,  KEISHIRO OKAMOTO ,  NOBUHIRO IMAIZUMI ,  TADAHIRO IMADA ,  KEIJI WATANABE

IPC分类号： H01L23/48

CPC分类号： H01L23/48 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/26175 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/29019 ,  H01L2224/29036 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/325 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/48744 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/13064 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83439 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0132 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.

摘要翻译： 半导体器件的制造包括在支撑板的半导体芯片安装区域和半导体芯片的后表面中的一个上形成具有第一金属的层和具有第二金属的层; 在第一金属层和第二金属层之间形成与第一金属层和第二金属层之间的一个区域对应的区域的另一层 的半导体芯片安装区域和半导体芯片的背面; 以及在将所述半导体芯片定位在所述半导体芯片安装区域中之后，形成与所述第一金属和所述第二金属合金的层，以将半导体芯片与半导体芯片安装区域接合。

公开(公告)号：US20140175678A1

公开(公告)日：2014-06-26

申请号：US14190366

申请日：2014-02-26

申请人： Renesas Electronics Corporation

发明人： Soshi Kuroda ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

IPC分类号： H01L23/00

CPC分类号： H01L24/46 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512

摘要： To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

摘要翻译： 为了实现半导体器件的成本降低，在公共板（布线板）中，多个接合引线各自朝向基板的中心延伸，并且作为支撑最小芯片的芯片接合区域的阻焊膜为 涂有芯片接合材料。 由此，即使安装作为大芯片的第一半导体芯片，也可以在不使芯片接合材料覆盖接合引线的情况下进行引线接合。 因此，可以降低开发成本以降低半导体器件（LGA）的成本。

公开(公告)号：US08741737B2

公开(公告)日：2014-06-03

申请号：US11858753

申请日：2007-09-20

申请人： Dan O. Popa ,  Rachita Dewan ,  Praveen Pandojirao-Sunkojirao ,  Jung-Chih Chiao

发明人： Dan O. Popa ,  Rachita Dewan ,  Praveen Pandojirao-Sunkojirao ,  Jung-Chih Chiao

IPC分类号： H01L21/30

CPC分类号： H01L25/0657 ,  B23K35/262 ,  B23K35/3013 ,  B23K35/3613 ,  C22C13/00 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2225/06517 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2924/00

摘要： Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a desired outcome. When fabricated, such vertically stacked structures include electrical interconnects provided by solder reflow. Solder reflow temperature is bounded by a curing and glass transition temperatures of a polymer used for bonding.

摘要翻译： 描述了具有一个或多个垂直互连的三维堆叠半导体结构。 垂直堆叠依赖于使用可图案化聚合物的垂直互连和晶圆接合。 聚合物优选是光刻图案和感光的。 根据期望的结果，聚合物的固化预先选自约35％至高达约100％。 当制造时，这种垂直堆叠的结构包括通过回流焊提供的电互连。 焊接回流温度受用于粘合的聚合物的固化和玻璃化转变温度的限制。

公开(公告)号：US08728867B2

公开(公告)日：2014-05-20

申请号：US13355792

申请日：2012-01-23

申请人： Kozo Shimizu ,  Keishiro Okamoto ,  Nobuhiro Imaizumi ,  Tadahiro Imada ,  Keiji Watanabe

发明人： Kozo Shimizu ,  Keishiro Okamoto ,  Nobuhiro Imaizumi ,  Tadahiro Imada ,  Keiji Watanabe

IPC分类号： H01L21/44

CPC分类号： H01L23/48 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/26175 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/29019 ,  H01L2224/29036 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/325 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/48744 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/13064 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83439 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0132 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.

摘要翻译： 半导体器件的制造包括在支撑板的半导体芯片安装区域和半导体芯片的后表面中的一个上形成具有第一金属的层和具有第二金属的层; 在第一金属层和第二金属层之间形成与第一金属层和第二金属层之间的一个区域对应的区域的另一层 的半导体芯片安装区域和半导体芯片的背面; 以及在将所述半导体芯片定位在所述半导体芯片安装区域中之后，形成与所述第一金属和所述第二金属合金的层，以将半导体芯片与半导体芯片安装区域接合。

公开(公告)号：US20140110866A1

公开(公告)日：2014-04-24

申请号：US14138333

申请日：2013-12-23

申请人： General Electric Company

发明人： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Laura A. Principe

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L23/562 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/92 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/17151 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.

摘要翻译： 公开了一种用于芯片封装制造的系统和方法。 芯片封装包括其中形成有开口的基底再分布层，具有形成在其中的没有粘合材料的窗口的粘合剂层和通过粘合剂层固定到基底再分布层的模具，模具是 与窗口对齐，使得只有模具的周边接触粘合剂层。 屏蔽元件位于基底再分布层和粘合剂层之间，该粘合剂层通常与形成在基底再分布层中的开口和粘合剂层的窗口对齐，使得仅屏蔽元件的周边附着到 粘合剂层。 屏蔽元件通过气隙与模具分离，并且被配置为可选择性地从粘合剂层移除以暴露模具的前表面。

公开(公告)号：US08614544B2

公开(公告)日：2013-12-24

申请号：US13383815

申请日：2010-05-28

申请人： Ryo Suzuki ,  Tadao Hayashi ,  Tomoya Tsukioka ,  Yoshikazu Takeuchi

发明人： Ryo Suzuki ,  Tadao Hayashi ,  Tomoya Tsukioka ,  Yoshikazu Takeuchi

IPC分类号： H01J1/00

CPC分类号： H01L33/38 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05552 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/06051 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12035 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

摘要： A light emitting device comprises a rectangular element mounted upon a mounting substrate via a heat-melted connecting material, wherein second substrate electrodes are formed conforming to the recesses of a first substrate electrode and a portion of the outer periphery of the first and second substrate electrodes is provided with first extended sections that extend farther outward than the outer periphery of the aforementioned element. The aforementioned first extended sections are formed in at least one or more locations per one side of the outer periphery of the aforementioned rectangular element; the aforementioned first substrate electrode is provided with second extended sections that are formed on at least one of both ends of the aforementioned recesses flanking the first extended sections of the aforementioned second substrate electrodes; and the aforementioned second extended sections extend farther outward than the outer periphery of the aforementioned element.

摘要翻译： 发光装置包括通过热熔融的连接材料安装在安装基板上的矩形元件，其中第二基板电极形成为符合第一基板电极的凹部和第一和第二基板电极的外周的一部分 设置有比上述元件的外周更向外延伸的第一延伸部。 上述第一延伸部分形成在上述矩形元件的外周的每一侧的至少一个或多个位置上; 上述第一基板电极设置有第二延伸部分，其形成在前述第二基板电极的第一延伸部分侧面的上述凹部的两端中的至少一个上; 并且上述第二延伸部分比上述元件的外周更向外延伸。

公开(公告)号：US08530278B2

公开(公告)日：2013-09-10

申请号：US13179468

申请日：2011-07-08

申请人： Nobuyasu Muto ,  Naoki Kawanabe ,  Hiroshi Ono ,  Tamaki Wada

发明人： Nobuyasu Muto ,  Naoki Kawanabe ,  Hiroshi Ono ,  Tamaki Wada

IPC分类号： H01L25/065 ,  H01L25/10 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L23/5388 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/743 ,  H01L24/78 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49429 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85191 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at.Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.

摘要翻译： 提高了半导体器件中的芯片布局的自由度，并且旨在提高封装密度。 由于可以通过通过球接合进行反向接合的过粘结而在存储芯片的焊盘上形成两个方向的线，因此可以通过球接合产生与楔形接合的连续接合接合相当的效果。 因此，可以提高芯片布局的自由度和基板3的引线布局的自由度，并且可以提高芯片层叠型半导体器件（存储卡）中的基板上的封装密度。