-
公开(公告)号：US20210327852A1
公开(公告)日：2021-10-21
申请号：US16851114
申请日：2020-04-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Chuan Teng , Victor Chiang Liang , Jung-Kuo Tu , Ching-Kai Shen
IPC: H01L25/065 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/00 , H01L25/00
Abstract: A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.
-
2.发明申请公开(公告)号：US20200098969A1
公开(公告)日：2020-03-26
申请号：US16413839
申请日：2019-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Alexander Kalnitsky , Chun-Ren Cheng , Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yan-Jie Liao
IPC: H01L41/08 , H01L41/047 , H01L41/297
Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.
-
公开(公告)号：US20200006469A1
公开(公告)日：2020-01-02
申请号：US16410259
申请日：2019-05-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Wen-Chuan Tai , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Anderson Lin , Fu-Chun Huang , Chun-Ren Cheng , Ivan Hua-Shu Wu , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.
-
4.发明授权公开(公告)号：US11730058B2
公开(公告)日：2023-08-15
申请号：US16413839
申请日：2019-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Alexander Kalnitsky , Chun-Ren Cheng , Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yan-Jie Liao
IPC: H01L41/193 , H01L41/08 , H01L41/113 , D01F6/62 , H10N30/00 , H10N30/04 , H10N30/067 , H10N30/87 , H10N30/063
CPC classification number: H10N30/10513 , H10N30/04 , H10N30/067 , H10N30/877 , H10N30/063
Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.
-
公开(公告)号：US11289568B2
公开(公告)日：2022-03-29
申请号：US16410259
申请日：2019-05-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Wen-Chuan Tai , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Anderson Lin , Fu-Chun Huang , Chun-Ren Cheng , Ivan Hua-Shu Wu , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.
-
Patent Agency Ranking
公开(公告)号：US11117796B2
公开(公告)日：2021-09-14
申请号：US16923869
申请日：2020-07-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Jung-Huei Peng , Shang-Ying Tsai , Hung-Chia Tsai , Yi-Chuan Teng
Abstract: An embodiment is a MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.
-
公开(公告)号：US20190135610A1
公开(公告)日：2019-05-09
申请号：US15873937
申请日：2018-01-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Chuan Teng , Chun-Yin Tsai , Chia-Hua Chu , Chun-Wen Cheng
Abstract: Structures and formation methods of a semiconductor device structure are provided. A semiconductor device structure includes a first dielectric layer and a second dielectric layer over a semiconductor substrate. A cavity penetrates through the first dielectric layer and the second dielectric layer. The semiconductor device structure also includes a first movable membrane between the first dielectric layer and the second dielectric layer. The first movable membrane is partially exposed through the cavity. The first movable membrane includes first corrugated portions arranged along an edge of the cavity.
-
公开(公告)号：US20140231967A1
公开(公告)日：2014-08-21
申请号：US13771382
申请日：2013-02-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Chuan Teng , Jung-Huei Peng , Shang-Ying Tsai , Hsin-Ting Huang , Lin-Min Hung , Yao-Te Huang , Chin-Yi Cho
CPC classification number: H01L21/185 , B81C1/00269 , B81C2201/053 , B81C2203/0118 , H01L21/561 , H01L21/563 , H01L23/3135 , H01L23/3185 , H01L23/564 , H01L29/06 , H01L2224/94 , H01L2924/18161 , H01L2224/83
Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.
Abstract translation: 公开了一种制造半导体器件的方法。 第一衬底被布置在第二衬底上。 在半导体器件上进行晶片接合处理。 设备的第一个区域由绑定过程包围。 设备的第二个区域保持暴露。 在进行晶片接合处理之后，在暴露的第二区域上执行一个或多个处理。 一个或多个过程包括在暴露的第二区域内形成填充材料的填充过程。 在执行一个或多个处理之后，在第一和第二基板上施加边缘密封材料。
-
公开(公告)号：US11274037B2
公开(公告)日：2022-03-15
申请号：US16937710
申请日：2020-07-24
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yang-Che Chen , Victor Chiang Liang , Chen-Hua Lin , Chwen-Ming Liu , Huang-Wen Tseng , Yi-Chuan Teng
Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.
-
10.发明授权公开(公告)号：US11107630B2
公开(公告)日：2021-08-31
申请号：US16417797
申请日：2019-05-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Anderson Lin , Chun-Ren Cheng , Chi-Yuan Shih , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Fu-Chun Huang , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC: H01G4/012 , H01G4/228 , H01L49/02 , H01L21/3213 , H01L21/311 , H01G4/12 , H01L41/113 , H01L41/083 , H01L41/047
Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
-
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.016 seconds)
