公开(公告)号：US20160163670A1

公开(公告)日：2016-06-09

申请号：US15040861

申请日：2016-02-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuei-Sung Chang ,  Nien-Tsung Tsai ,  Ting-Hau Wu ,  Yi Heng Tsai

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05082 ,  H01L2224/26145 ,  H01L2224/2745 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29193 ,  H01L2224/32506 ,  H01L2224/83097 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00012

Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.

公开(公告)号：US09287440B2

公开(公告)日：2016-03-15

申请号：US13942112

申请日：2013-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC: H01L31/00 ,  H01L33/00 ,  H01L21/683 ,  H01L23/48 ,  H01L33/48 ,  H01L33/62 ,  H01L33/64 ,  H01L21/768 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底中形成第一开口和第二开口。 该方法还包括在第一开口中形成导电材料，并且在第二开口中，导电材料包括接合部分，其中第一开口中的导电材料和第二开口中的导电材料以第一开口电连接和热连接在一起 基板的表面。 该方法还包括从衬底的与第一表面相对的第二表面减小衬底的厚度，以暴露第一开口中的导电材料和第二开口中的导电材料。 该方法还包括将器件连接到衬底的第二表面。

公开(公告)号：US08946742B2

公开(公告)日：2015-02-03

申请号：US12897124

申请日：2010-10-04

Applicant: Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

Inventor： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC: H01L33/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/48 ,  H01L33/48 ,  H01L33/64 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L33/62

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

Abstract translation: 具有上述通孔硅衬底（或通孔）的基板消除了对导电凸块的需要。 流程非常简单，成本效益高。 所描述的结构将单独的TSV，再分配层和导电凸块结构组合成单个结构。 通过组合单独的结构，产生具有高散热能力的低电阻电连接。 此外，具有通过硅插头（或通孔或沟槽）的基板还允许将多个芯片封装在一起。 通过硅沟槽可围绕一个或多个芯片，以在制造期间提供防止铜扩散到相邻器件的保护。 此外，具有相似或不同功能的多个芯片可以集成在TSV基板上。 通过具有不同图案的硅插头可以在半导体芯片下使用以改善散热并解决制造问题。

公开(公告)号：US08841772B2

公开(公告)日：2014-09-23

申请号：US13777670

申请日：2013-02-26

Applicant: Panasonic Corporation

Inventor： Yoshiaki Shimizu ,  Yuichiro Yamada ,  Toshiyuki Fukuda

IPC: H01L23/00

CPC classification number: H05K3/38 ,  B29C43/18 ,  B29C45/02 ,  B29C45/14655 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/3511 ,  H05K3/3457 ,  H05K2201/0379 ,  H05K2201/10515 ,  H05K2201/10977 ,  H05K2203/0278 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00012 ,  H01L2924/0695

Abstract: A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode 9 is formed in a region outside of an element mounting region of a substrate 5. The projected electrode 9 includes a protruding portion that protrudes from the front face of a molding resin portion 10. The distal end of the protruding portion is a flat face 13. In addition, a portion of the projected electrode 9 whose cross section is larger than the protruding portion is positioned inside the molding resin portion 10.

Abstract translation: 提供能够实现高度可靠的三维安装的半导体器件及其制造方法。 突起电极9形成在基板5的元件安装区域的外侧的区域中。突出电极9包括从模制树脂部分10的前表面突出的突出部分。突出部分的远端是 另外，突出电极9的横截面大于突出部分的部分位于模制树脂部分10的内部。

公开(公告)号：US20140117510A1

公开(公告)日：2014-05-01

申请号：US13660374

申请日：2012-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, L

Inventor： Kuei-Sung Chang ,  Nien-Tsung Tsai ,  Ting-Hau Wu ,  Yi Heng Tsai

IPC: H01L29/02 ,  H01L21/762

CPC classification number: H01L24/29 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05082 ,  H01L2224/26145 ,  H01L2224/2745 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29193 ,  H01L2224/32506 ,  H01L2224/83097 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00012

Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.

Abstract translation: 提供一种用于接合半导体器件的系统和方法。 一个实施方案包括通过以栅格图案提供其中一种反应物的附加材料来停止共晶粘合材料的流动，使得当共晶材料流入附加材料时，附加材料将改变流动共晶材料的组成 并使材料固化，从而停止流动。 其他实施例提供了额外的布局以将附加材料放入流动共晶材料的路径中。

公开(公告)号：US08507940B2

公开(公告)日：2013-08-13

申请号：US12879584

申请日：2010-09-10

Applicant: Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

Inventor： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC: H01L33/00

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.

Abstract translation: 具有上述通孔硅封装（或通孔）的封装衬底为需要热管理的半导体芯片提供侧向和垂直散热​​路径。 具有高占空比的通过硅插头（TSP）的设计可以最有效地提供散热。 具有双面梳状图案的TSP设计可以提供等于或大于50％的高占空比。 具有高占空比的封装衬底对于产生大量热量的半导体芯片是有用的。 这种半导体芯片的例子是发光二极管（LED）芯片。

公开(公告)号：US08481368B2

公开(公告)日：2013-07-09

申请号：US13092059

申请日：2011-04-21

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L21/44

CPC classification number: H01L24/49 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/13099 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32506 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73153 ,  H01L2224/73255 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Abstract translation: 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US08470640B2

公开(公告)日：2013-06-25

申请号：US12165297

申请日：2008-06-30

Applicant: Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

IPC: H01L21/00

CPC classification number: H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04953 ,  H01L2924/078 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.

Abstract translation: 公开了半导体管芯和低剖面半导体封装的制造方法。 半导体封装可以包括安装到衬底的至少第一和第二堆叠半导体管芯。 第一和/或第二半导体管芯可以沿着半导体管芯的侧边缘通过半导体管芯的底表面被制造成具有局部空腔。 一个侧面中的一个或多个局部空腔占据整个侧面。 因此，局部空腔允许半导体芯片的低高度堆叠，同时为每个模具提供高度的结构完整性，以防止在制造期间模头边缘的破裂或断裂。

公开(公告)号：US08399969B2

公开(公告)日：2013-03-19

申请号：US12844590

申请日：2010-07-27

Applicant: Kuo-Ching Chang ,  Wu-Cheng Kuo ,  Tzu-Han Lin

Inventor： Kuo-Ching Chang ,  Wu-Cheng Kuo ,  Tzu-Han Lin

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L24/33 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/04042 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32506 ,  H01L2224/335 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12035 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Abstract translation: 提供了芯片封装及其制造方法。 芯片封装包括衬底和布置在衬底上的芯片。 焊料层设置在芯片和衬底之间。 导电焊盘设置在焊料层和衬底之间，其中导电焊盘包括布置在焊料层下方的第一部分，远离第一部分设置的第二部分和设置在第一部分和第二部分之间的连接部分。 连接部分的宽度比沿着从第一部分延伸到连接部分的第二方向垂直的第一方向的第一部分的宽度窄。

公开(公告)号：US08252632B2

公开(公告)日：2012-08-28

申请号：US13156280

申请日：2011-06-08

Applicant: Yuichi Yato ,  Takuya Nakajo ,  Hiroi Oka

Inventor： Yuichi Yato ,  Takuya Nakajo ,  Hiroi Oka

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L24/83 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/743 ,  H01L24/84 ,  H01L2224/04026 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/32506 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83194 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/83205 ,  H01L2924/00012

Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).

Abstract translation: 本发明能够提高插入在半导体芯片和芯片焊盘部之间的导电性粘合剂的接合可靠性。 提供了一种半导体器件，其中硅芯片安装在与漏极引线一体形成的芯片焊盘部分上方，在主表面上具有源极焊盘，在背面上具有功率MOSFET的漏电极，并且被接合到 通过Ag浆料的芯片焊盘部分。 在器件中，源极引线和源极焊盘通过铝带电耦合。 在硅芯片的背面上形成Ag纳米颗粒涂层膜，而在芯片焊盘部分和引线（漏极引线和源极引线）之上形成另一Ag纳米颗粒涂覆膜。