发明授权
- 专利标题： Three-dimensional wafer stacking with vertical interconnects
- 专利标题（中）： 具有垂直互连的三维晶片堆叠
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申请号： US11858753申请日： 2007-09-20
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公开(公告)号： US08741737B2公开(公告)日： 2014-06-03
- 发明人: Dan O. Popa , Rachita Dewan , Praveen Pandojirao-Sunkojirao , Jung-Chih Chiao
- 申请人： Dan O. Popa , Rachita Dewan , Praveen Pandojirao-Sunkojirao , Jung-Chih Chiao
- 申请人地址： US TX Austin
- 专利权人： Board of Regents, The University of Texas System
- 当前专利权人： Board of Regents, The University of Texas System
- 当前专利权人地址： US TX Austin
- 代理机构： Crowdhury & Georgakis, P.C.
- 主分类号： H01L21/30
- IPC分类号： H01L21/30
摘要：
Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a desired outcome. When fabricated, such vertically stacked structures include electrical interconnects provided by solder reflow. Solder reflow temperature is bounded by a curing and glass transition temperatures of a polymer used for bonding.
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