公开(公告)号：US20240222302A1

公开(公告)日：2024-07-04

申请号：US18552746

申请日：2021-07-19

申请人： ORBOTECH LTD.

发明人： Zvi KOTLER ,  Ofer FOGEL ,  Sharona COHEN ,  Gil BERNSTEIN TOKER ,  Niv GORODESKY

IPC分类号： H01L23/00 ,  B23K1/00 ,  B23K1/005 ,  B23K3/047 ,  B23K3/06 ,  B23K3/08 ,  B23K101/40 ,  H01L21/66

CPC分类号： H01L24/11 ,  B23K1/0016 ,  B23K1/0056 ,  B23K3/047 ,  B23K3/0638 ,  B23K3/08 ,  H01L22/20 ,  H01L24/742 ,  B23K2101/40 ,  H01L2224/11318 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/742

摘要： A method for circuit fabrication includes inspecting an array of solder bumps on a circuit substrate so as to identify a solder bump having a height above the substrate that is greater than a predefined maximum. A first laser beam is directed toward the identified solder bump so as to ablate a selected amount of a solder material from the identified solder bump. Alternatively or additionally, a further solder bump having a height above the substrate that is less than a predefined minimum is identified, and one or more molten droplets of the solder material are deposited on the further solder bump. After ablating or depositing the solder material, a second laser beam is directed toward the identified solder bump with sufficient energy to cause the solder material in the identified solder bump to melt and reflow.

公开(公告)号：US20170125332A1

公开(公告)日：2017-05-04

申请号：US14634547

申请日：2015-02-27

申请人： QUALCOMM Incorporated

发明人： Young Kyu Song ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L21/4857 ,  H01G4/12 ,  H01G4/224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

公开(公告)号：US20160218076A1

公开(公告)日：2016-07-28

申请号：US14870377

申请日：2015-09-30

申请人： Kabushiki Kaisha Toshiba

发明人： Nobuto MANAGAKI ,  Hiroshi YAMADA

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L24/13 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/1183 ,  H01L2224/11848 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13011 ,  H01L2224/13025 ,  H01L2224/13553 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/24195 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/19105

摘要： According to one embodiment, a semiconductor device includes a first conductive portion, a second conductive portion, a first layer, and a second layer. The first conductive portion includes a first end portion and a first extending portion. The first extending portion extends in a first direction. The length of the first extending portion in a second direction is shorter than a length of at least a part of the first end portion in the second direction. The first layer includes multiple semiconductor chips, multiple passive chip components, and a resin. The first extending portion includes a first portion and a second portion. The first layer is provided around the first portion. The first layer expands along a first plane. The first plane intersects the first direction. The second layer includes a first multilayer wiring. The second layer expands along a second plane intersecting the first direction.

摘要翻译： 根据一个实施例，半导体器件包括第一导电部分，第二导电部分，第一层和第二层。 第一导电部分包括第一端部和第一延伸部分。 第一延伸部分在第一方向上延伸。 第一延伸部分在第二方向上的长度短于第一端部在第二方向上的至少一部分的长度。 第一层包括多个半导体芯片，多个无源芯片组件和树脂。 第一延伸部分包括第一部分和第二部分。 第一层围绕第一部分设置。 第一层沿第一平面扩展。 第一个平面与第一个方向相交。 第二层包括第一多层布线。 第二层沿与第一方向相交的第二平面膨胀。

公开(公告)号：US20150162291A1

公开(公告)日：2015-06-11

申请号：US14098218

申请日：2013-12-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHIA-CHUN MIAO ,  SHIH-WEI LIANG ,  KAI-CHIANG WU ,  YEN-PING WANG

IPC分类号： H01L23/00

CPC分类号： H01L23/564 ,  H01L23/16 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/03828 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2224/81 ,  H01L2224/03

摘要： A semiconductor device having a semiconductor substrate is provided. The semiconductor device has a metal structure over the semiconductor substrate. The metal structure is configured to receive a bump. The semiconductor device further has a conductive trace between the semiconductor substrate and the metal structure. The conductive trace is configured to connect to a power source. When an electric current from the power source passes through the conductive trace, an electromagnetic field is generated at the conductive trace. The position of the bump is adjusted in response to the electromagnetic field.

摘要翻译： 提供了具有半导体衬底的半导体器件。 半导体器件在半导体衬底上具有金属结构。 金属结构构造成接收凸起。 半导体器件还在半导体衬底和金属结构之间具有导电迹线。 导电迹线被配置为连接到电源。 当来自电源的电流通过导电迹线时，在导电迹线处产生电磁场。 凸起的位置响应于电磁场而被调节。

公开(公告)号：US08994174B2

公开(公告)日：2015-03-31

申请号：US13994660

申请日：2011-09-30

申请人： Kevin J. Lee

发明人： Kevin J. Lee

IPC分类号： H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/11848 ,  H01L21/304

摘要： A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.

摘要翻译： 描述了在贯穿硅通孔（TSV）处理期间处理器件晶片的结构和方法，其中器件晶片通过永久性热固性材料结合到临时支撑衬底。 在移除临时支撑基板时，露出包括回流焊料凸块和永久性热固性材料的平面前沿接合表面。

公开(公告)号：US20140167252A1

公开(公告)日：2014-06-19

申请号：US13718130

申请日：2012-12-18

申请人： Maxim Integrated Products, Inc.

发明人： Karthik Thambidurai ,  Viren Khandekar ,  Tiao Zhou

IPC分类号： H01L21/48 ,  H01L23/488 ,  H01L21/82

CPC分类号： H01L21/4814 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/743 ,  H01L24/93 ,  H01L24/94 ,  H01L2224/0381 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11422 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may enable ultra-thin wafer-level packages (WLP), ultra-thin wafer level quad-flat no-leads (WQFN) packages, or the like.

摘要翻译： 这里描述了用于浸焊工艺的技术，其提供了可以实施以促进封装厚度缩放（例如，减小整个封装厚度）的低轮廓，低成本的焊料凸块形成工艺。 例如，本文公开的浸焊方法可以实现超薄晶片级封装（WLP），超薄晶片级四平面无引线（WQFN）封装等。

公开(公告)号：US20140151698A1

公开(公告)日：2014-06-05

申请号：US13691439

申请日：2012-11-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY, LTD.

发明人： Hsien-Wei Chen ,  Jie Chen

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/1183 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13455 ,  H01L2224/13464 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/05552

摘要： An integrated circuit structure includes a passivation layer, a polymer layer over the passivation layer, and a PPI monitor structure. The PPI monitor structure includes a portion overlying a portion of the polymer layer. The PPI monitor structure is electrically floating.

摘要翻译： 集成电路结构包括钝化层，钝化层上的聚合物层和PPI监测器结构。 PPI监测器结构包括覆盖聚合物层的一部分的部分。 PPI监视器结构是电浮动的。

公开(公告)号：US20140021596A1

公开(公告)日：2014-01-23

申请号：US13551610

申请日：2012-07-18

申请人： Yat Kit Tsui ,  Dan Yang ,  Pui Chung Law

发明人： Yat Kit Tsui ,  Dan Yang ,  Pui Chung Law

IPC分类号： H01L23/485 ,  H01L21/60 ,  H01L23/08

CPC分类号： H01L27/14618 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/10156 ,  H01L2224/1132 ,  H01L2224/1182 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13565 ,  H01L2224/1369 ,  H01L2224/16106 ,  H01L2224/16108 ,  H01L2224/16148 ,  H01L2224/16157 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/81895 ,  H01L2224/9202 ,  H01L2224/92222 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/19 ,  H01L21/78 ,  H01L2924/00

摘要： The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

摘要翻译： 本发明涉及在晶片级封装的半导体器件，使得在分离各个器件之前形成整个封装器件。 半导体器件封装包括具有与芯片相关联的一个或多个焊盘和半导体芯片上粘合的保护层的半导体芯片。 绝缘层位于半导体芯片的至少侧边缘和下表面上。 互连/凸起金属化位于与半导体芯片的一个或多个侧边相邻并且与至少一个接合焊盘电连接。 可以形成紧凑的图像传感器封装，其与数字信号处理器和存储器芯片一起与透镜和保护盖垂直集成。

公开(公告)号：US07867842B2

公开(公告)日：2011-01-11

申请号：US12181852

申请日：2008-07-29

申请人： Peter Alfred Gruber ,  Paul Alfred Lauro ,  Jae-Woong Nah

发明人： Peter Alfred Gruber ,  Paul Alfred Lauro ,  Jae-Woong Nah

IPC分类号： H01L21/8242

CPC分类号： B23K1/0016 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11848 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T428/24612 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier including at least a first decal including a first plurality of openings and a second decal including a second plurality of openings, the first and second decals being arranged such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy to thereby form at least first and second plugs, the first plug having a first surface and a second surface substantially parallel to one another, the second plug having a third surface and a fourth surface substantially parallel to one another; removing at least one of the first and second decals to at least partially expose the first and second plugs; aligning the alloy carrier with the receiving substrate so that the first and second plugs correspond to the selected areas on the receiving substrate; and transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas.

公开(公告)号：US20090294961A1

公开(公告)日：2009-12-03

申请号：US12131541

申请日：2008-06-02

申请人： Thorsten Meyer ,  Recai Sezi ,  Markus Brunnbauer

发明人： Thorsten Meyer ,  Recai Sezi ,  Markus Brunnbauer

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/27 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/116 ,  H01L2224/1183 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/27462 ,  H01L2224/73104 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

摘要： A semiconductor device includes a semiconductor chip and a metal layer electrically coupled to the semiconductor chip. The semiconductor device includes an array of solder balls coupled to the metal layer and a front side protect material directly contacting the metal layer and laterally surrounding a portion of at least a plurality of solder balls. The front side protect material is configured to become fluid during solder reflow.

摘要翻译： 半导体器件包括电连接到半导体芯片的半导体芯片和金属层。 半导体器件包括耦合到金属层的焊料球阵列和直接接触金属层并横向围绕至少多个焊球的一部分的前侧保护材料。 正面保护材料配置成在回流焊时成为流体。