公开(公告)号：US20240304581A1

公开(公告)日：2024-09-12

申请号：US18279487

申请日：2022-02-22

Applicant: NanoWired GmbH

Inventor： Olav Birlem ,  Florian Dassinger ,  Sebastian Quednau ,  Farough Roustaie

IPC: H01L23/00 ,  H05K3/28 ,  H05K3/36

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H05K3/282 ,  H05K3/368 ,  H01L2224/11823 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1357 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13693 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81897

Abstract: Method for applying a coating to a plurality of nanowires on a component, the method comprising:



a) treating the nanowires with a reducing substance,
b) immersing the nanowires in a protective substance,
c) drying the nanowires, so that the coating is obtained from the protective substance.

公开(公告)号：US09716066B2

公开(公告)日：2017-07-25

申请号：US14779022

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  James Y. Jeong ,  Hsiao-Kang Chang ,  John Muirhead ,  Adwait Telang ,  Puneesh Puri ,  Jiho Kang ,  Nitin M. Patel

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

公开(公告)号：US20170025391A1

公开(公告)日：2017-01-26

申请号：US15288751

申请日：2016-10-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/038 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05693 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48693 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48793 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48893 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01006

Abstract: Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Abstract translation: 实施例涉及包装封装（PoP）结构，包括柱状灯泡和形成PoP结构的方法。 根据实施例，结构包括第一基板，螺柱灯泡，模具，第二基板和电连接器。 螺柱灯泡耦合到第一基板的第一表面。 模具附接到第一基板的第一表面。 电连接器耦合到第二基板，并且相应的电连接器耦合到相应的螺柱灯泡。

公开(公告)号：US20160218076A1

公开(公告)日：2016-07-28

申请号：US14870377

申请日：2015-09-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Nobuto MANAGAKI ,  Hiroshi YAMADA

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L24/13 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/1183 ,  H01L2224/11848 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13011 ,  H01L2224/13025 ,  H01L2224/13553 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/24195 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/19105

Abstract: According to one embodiment, a semiconductor device includes a first conductive portion, a second conductive portion, a first layer, and a second layer. The first conductive portion includes a first end portion and a first extending portion. The first extending portion extends in a first direction. The length of the first extending portion in a second direction is shorter than a length of at least a part of the first end portion in the second direction. The first layer includes multiple semiconductor chips, multiple passive chip components, and a resin. The first extending portion includes a first portion and a second portion. The first layer is provided around the first portion. The first layer expands along a first plane. The first plane intersects the first direction. The second layer includes a first multilayer wiring. The second layer expands along a second plane intersecting the first direction.

Abstract translation: 根据一个实施例，半导体器件包括第一导电部分，第二导电部分，第一层和第二层。 第一导电部分包括第一端部和第一延伸部分。 第一延伸部分在第一方向上延伸。 第一延伸部分在第二方向上的长度短于第一端部在第二方向上的至少一部分的长度。 第一层包括多个半导体芯片，多个无源芯片组件和树脂。 第一延伸部分包括第一部分和第二部分。 第一层围绕第一部分设置。 第一层沿第一平面扩展。 第一个平面与第一个方向相交。 第二层包括第一多层布线。 第二层沿与第一方向相交的第二平面膨胀。

公开(公告)号：US09379084B2

公开(公告)日：2016-06-28

申请号：US14682914

申请日：2015-04-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L33/62

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.

公开(公告)号：US09331040B2

公开(公告)日：2016-05-03

申请号：US14429364

申请日：2013-07-19

Applicant: Atotech Deutschland GmbH

Inventor： Thomas Beck ,  Gerhard Steinberger ,  Andreas Walter

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11821 ,  H01L2224/11822 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/16507 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3841 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01042 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/05552

Abstract: The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar.

Abstract translation: 本发明涉及一种用于在半导体衬底上形成铜柱的方法，所述铜柱具有底部金属化区域，所述底部衬底金属化区域包括比铜更贵的金属，并且可选地在顶部上具有焊料凸块，并且具有第二金属层 选自沉积在所述铜柱的侧壁上的锡，锡合金，银和银合金。 在沉积第二金属层之前，将比铜更贵的第一金属层沉积在铜柱的整个外表面上。 然后，第二金属层至少具有减少数量的不期望的针孔，并且用作下面的铜柱的保护层。

公开(公告)号：US20160104685A1

公开(公告)日：2016-04-14

申请号：US14976927

申请日：2015-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Ming-Fa Chen ,  Rung-De Wang

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/11831 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/35 ,  Y10T428/12361 ,  Y10T428/12396 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

Abstract: A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.

Abstract translation: 一种装置包括：包括金属凸块的工件; 以及具有直接在金属凸块上的部分的介电层。 金属凸块和电介质层部分的表面形成界面。 在金属凸块上方形成金属涂层并与金属凸块接触。 金属表面从介电层上延伸到界面的下方。

公开(公告)号：US09287190B2

公开(公告)日：2016-03-15

申请号：US14337977

申请日：2014-07-22

Applicant: International Business Machines Corporation

Inventor： Daniel J. Buvid ,  Eric J. Campbell ,  Tyler Jandt ,  Joseph Kuczynski

IPC: H01L23/36 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/3107 ,  H01L23/29 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/3171 ,  H01L23/367 ,  H01L23/373 ,  H01L23/44 ,  H01L23/473 ,  H01L23/564 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/11821 ,  H01L2224/11823 ,  H01L2224/11826 ,  H01L2224/11827 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/742 ,  H01L2224/8192 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/16151 ,  H01L2924/16251 ,  H01L2924/181 ,  H05K1/0203 ,  H05K7/20236 ,  H05K2201/064 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/01049 ,  H01L2924/01048 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Devices employing semiconductor die having hydrophobic coatings, and related cooling methods are disclosed. A device may include at least one semiconductor die electrically coupled to a substrate by electrical contact elements. During operation the semiconductor die and the electrical contact elements generate heat. By applying hydrophobic coatings to the semiconductor die and the electrical contact elements, a cooling fluid may be used to directly cool the semiconductor die and the electrical contact elements to maintain these components within temperature limits and free from electrical shorting and corrosion. In this manner, the semiconductor die and associated electrical contact elements may be cooled to avoid the creation of damaging localized hot spots and temperature-sensitive semiconductor performance issues.

公开(公告)号：US20150279797A1

公开(公告)日：2015-10-01

申请号：US14429364

申请日：2013-07-19

Applicant: ATOTECH DEUTSCHLAND GMBH

Inventor： Thomas Beck ,  Gerhard Steinberger ,  Andreas Walter

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11821 ,  H01L2224/11822 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/16507 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3841 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01042 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/05552

Abstract: The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar.

Abstract translation: 本发明涉及一种用于在半导体衬底上形成铜柱的方法，所述铜柱具有底部金属化区域，所述底部衬底金属化区域包括比铜更贵的金属，并且可选地在顶部上具有焊料凸块，并且具有第二金属层 选自沉积在所述铜柱的侧壁上的锡，锡合金，银和银合金。 在沉积第二金属层之前，将比铜更贵的第一金属层沉积在铜柱的整个外表面上。 然后，第二金属层至少具有减少数量的不期望的针孔，并且用作下面的铜柱的保护层。

公开(公告)号：US20150214182A1

公开(公告)日：2015-07-30

申请号：US14682914

申请日：2015-04-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯。 衬底具有互连部位的导电迹线。 导电凸块材料沉积在互连部位或模具凸块焊盘上。 将半导体管芯安装在衬底上，使得凸块材料设置在管芯凸块焊盘和互连部位之间。 凸块材料在管芯凸块焊盘或互连部位周围没有焊接掩模回流，以在管芯和衬底之间形成互连结构。 凸起材料在管芯凸块焊盘或互连部位内自我限制。 凸起材料的体积被选择为使得表面张力基本上保持凸块材料的自限制在模具凸块焊盘和互连部位的覆盖区内。 互连结构可以具有可熔部分和不可熔部分。 封装剂沉积在管芯和衬底之间。