公开(公告)号：US09824991B2

公开(公告)日：2017-11-21

申请号：US15421340

申请日：2017-01-31

申请人： INTEL CORPORATION

发明人： Aleksandar Aleksov ,  Tony Dambrauskas ,  Danish Faruqui ,  Mark S. Hlad ,  Edward R. Prack

IPC分类号： H01L21/58 ,  H01L23/00 ,  H01L21/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/02118 ,  H01L21/02263 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76883 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3142 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81375 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81913 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.

公开(公告)号：US20170025391A1

公开(公告)日：2017-01-26

申请号：US15288751

申请日：2016-10-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/038 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05693 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48693 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48793 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48893 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01006

摘要： Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

摘要翻译： 实施例涉及包装封装（PoP）结构，包括柱状灯泡和形成PoP结构的方法。 根据实施例，结构包括第一基板，螺柱灯泡，模具，第二基板和电连接器。 螺柱灯泡耦合到第一基板的第一表面。 模具附接到第一基板的第一表面。 电连接器耦合到第二基板，并且相应的电连接器耦合到相应的螺柱灯泡。

公开(公告)号：US20160155667A1

公开(公告)日：2016-06-02

申请号：US15018686

申请日：2016-02-08

申请人： INTEL CORPORATION

发明人： Aleksandar ALEKSOV ,  Tony DAMBRAUSKAS ,  Danish FARUQUI ,  Mark S. HLAD ,  Edward R. PRACK

IPC分类号： H01L21/78 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L21/027

CPC分类号： H01L24/11 ,  H01L21/02118 ,  H01L21/02263 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76883 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3142 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81375 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81913 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.

摘要翻译： 描述了电子组件及其制造。 一个实施例涉及一种方法，包括在半导体晶片上的金属凸块上沉积有机薄膜层，该有机薄膜层也形成在与晶片上的金属凸块相邻的表面上。 将晶片切割成多个半导体管芯结构，该管芯结构包括有机薄膜层。 半导体管芯结构附着到基板上，其中，附接包括在管芯结构上的金属凸块和衬底上的焊盘之间形成焊料接合，并且其中焊料接合延伸穿过有机薄膜层。 然后将有机薄膜层暴露于等离子体。 描述和要求保护其他实施例。

公开(公告)号：US09030001B2

公开(公告)日：2015-05-12

申请号：US14058955

申请日：2013-10-21

申请人： Tessera, Inc.

发明人： Belgacem Haba

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L21/50 ,  B82Y40/00

CPC分类号： H01L24/17 ,  B82Y40/00 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/49811 ,  H01L23/52 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/116 ,  H01L2224/1182 ,  H01L2224/11821 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13794 ,  H01L2224/13911 ,  H01L2224/13944 ,  H01L2224/13947 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/81026 ,  H01L2224/81099 ,  H01L2224/81143 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  Y10S977/773 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof.

摘要翻译： 制造组件的方法包括以下步骤：将金属纳米颗粒施加到第一部件和第二部件中的任一个或两者的导电元件的暴露表面上，将第一部件的导电元件与第二部件的导电元件并置， 设置在其间的金属纳米颗粒，并且至少在并置的导电元件的界面处将温度升高到金属纳米粒子在并置的导电元件之间形成冶金接合部的接合温度。 第一部件和第二部件中的任一个或两者的导电元件可以包括基本上刚性的支柱，其具有突出在相应部件的表面上方的高度的顶表面，并且远离其顶表面以基本角度延伸的边缘表面。

公开(公告)号：US20120329182A1

公开(公告)日：2012-12-27

申请号：US13512955

申请日：2011-10-26

申请人： Teppei Kojio ,  Masashi Matsumori ,  Tadahiko Sakai ,  Takatoshi Ishikawa

发明人： Teppei Kojio ,  Masashi Matsumori ,  Tadahiko Sakai ,  Takatoshi Ishikawa

IPC分类号： H01L21/607 ,  H01L33/52 ,  H01L33/62 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/75 ,  H01L24/97 ,  H01L33/62 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/758 ,  H01L2224/75842 ,  H01L2224/81002 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81447 ,  H01L2224/83205 ,  H01L2224/83207 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2933/0066 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： When metal junction between a first electrode and a second electrode is executed as ultrasonic bonding between metals including at least copper, the ultrasonic bonding is performed in a state that a contact interface between the first electrode and the second electrode is covered with a bonding auxiliary agent. As a result, formation of oxide at a bonding interface between the first electrode and the second electrode due to execution of the ultrasonic bonding can be suppressed. Therefore, while a desired bonding strength is ensured, ultrasonic bonding with copper used for the first electrode or the second electrode can be fulfilled and cost cuts in mounting of semiconductor devices can be achieved.

摘要翻译： 当第一电极和第二电极之间的金属接合作为至少包括铜的金属之间的超声波接合被执行时，在第一电极和第二电极之间的接触界面被接合助剂覆盖的状态下进行超声波接合 。 结果，可以抑制由于执行超声波接合而在第一电极和第二电极之间的接合界面处的氧化物的形成。 因此，在确保期望的接合强度的情况下，可以实现与第一电极或第二电极所使用的铜的超声波接合，并且可以实现半导体器件的安装成本降低。

公开(公告)号：US08013256B2

公开(公告)日：2011-09-06

申请号：US12261517

申请日：2008-10-30

申请人： Toru Nakai

发明人： Toru Nakai

IPC分类号： H05K1/09

CPC分类号： H05K1/115 ,  C23C18/54 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/538 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H05K1/112 ,  H05K3/244 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/383 ,  H05K3/4602 ,  H05K3/4644 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05599

摘要： A printed wiring board including solder pads excellent in frequency characteristic is provided. To do so, each solder pad 73 is formed by providing a single tin layer 74 on a conductor circuit 158 or a via 160. Therefore, a signal propagation rate can be increased, as compared with a printed wiring board of the prior art on which two metal layers are formed. In addition, due to lack of nickel layers, manufacturing cost can be decreased and electric characteristics can be enhanced.

摘要翻译： 提供了包括频率特性优异的焊盘的印刷线路板。 为此，通过在导体电路158或通孔160上设置单个锡层74来形成每个焊盘73.因此，与现有技术的印刷电路板相比，可以增加信号传播速率 形成两个金属层。 此外，由于缺乏镍层，可以降低制造成本，并且可以提高电特性。

公开(公告)号：US20090026615A1

公开(公告)日：2009-01-29

申请号：US12177458

申请日：2008-07-22

申请人： Fumiyoshi Kawashiro

发明人： Fumiyoshi Kawashiro

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/81 ,  H01L23/60 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13553 ,  H01L2224/13566 ,  H01L2224/13686 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/81026 ,  H01L2224/81047 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K3/3457 ,  H05K2203/0221 ,  H05K2203/0315 ,  H01L2924/01083 ,  H01L2924/053 ,  H01L2224/29099 ,  H01L2924/00

摘要： In one embodiment, a semiconductor device has a semiconductor element made up of a semiconductor chip, first solder balls provided on the semiconductor chip and a BGA substrate on which the semiconductor chip is mounted via the first solder balls. Furthermore, the semiconductor device has external terminals on a surface of the BGA substrate opposing to a surface on which the semiconductor chip is mounted. The external terminals include oxide films provided with through holes.

摘要翻译： 在一个实施例中，半导体器件具有由半导体芯片，设置在半导体芯片上的第一焊球和经由第一焊球安装半导体芯片的BGA基板构成的半导体元件。 此外，半导体器件在BGA衬底的与安装有半导体芯片的表面相对的表面上具有外部端子。 外部端子包括设置有通孔的氧化物膜。

公开(公告)号：US20030127499A1

公开(公告)日：2003-07-10

申请号：US10040740

申请日：2002-01-07

申请人： International Business Machines Corporation

发明人： Mark V. Pierson ,  Ajit K. Trivedi

IPC分类号： B23K035/12

CPC分类号： H05K3/3436 ,  B23K26/0006 ,  B23K26/361 ,  B23K2101/42 ,  B23K2103/16 ,  H01L23/49816 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81026 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/3457 ,  H05K2201/09745 ,  H05K2201/10992 ,  H05K2203/0278 ,  H05K2203/048 ,  Y02P70/613 ,  H01L2924/00

摘要： Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.

摘要翻译： 提供了基板与芯片的自对准组合，在相应的基板和芯片表面上使用凸起凹槽和凸起形状的反向图案。 避免了大力接触凸块生产。 实现芯片和基板之间的可靠接触，并且在芯片放置之后使偏移最小化。

公开(公告)号：US20030022477A1

公开(公告)日：2003-01-30

申请号：US10052989

申请日：2001-11-09

发明人： Han-Kun Hsieh ,  Shing-Ru Wang ,  I-Chung Tung

IPC分类号： H01L021/44

CPC分类号： H01L24/16 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/0094 ,  H05K3/3473 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of fabricating electroplate solder on an organic circuit board for forming flip chip joints and board to board solder joints is disclosed. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact pad. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by eletroplating. Finally, the resist and the metal seed layer beneath the resist are removed.

摘要翻译： 公开了一种在用于形成倒装芯片接头和板对板焊点的有机电路板上制造电镀焊料的方法。 在该方法中，最初提供了一种有机电路板，其包括具有至少一个接触垫的表面承载电路。 焊接掩模层，其被放置在板表面上并被图案化以暴露焊盘。 随后，在板表面上通过物理气相沉积，化学气相沉积，使用催化铜的化学镀或使用催化铜的电镀沉积金属种子层。 在金属种子层上形成具有至少位于焊盘处的开口的抗蚀剂层。 然后通过电镀在开口中形成焊料。 最后，去除抗蚀剂下的抗蚀剂和金属种子层。

公开(公告)号：US12027487B2

公开(公告)日：2024-07-02

申请号：US18145310

申请日：2022-12-22

申请人： ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

发明人： Cyprian Emeka Uzoh

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13084 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/13684 ,  H01L2224/13686 ,  H01L2224/13805 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16265 ,  H01L2224/16268 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81026 ,  H01L2224/81065 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/83026 ,  H01L2224/83815 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3841

摘要： A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.