公开(公告)号：US12002783B2

公开(公告)日：2024-06-04

申请号：US17548205

申请日：2021-12-10

申请人： SK hynix Inc.

发明人： Jun Yong Song ,  Kang Hun Kim ,  Si Yun Kim

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/10175 ,  H01L2224/11013 ,  H01L2224/1146 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13147 ,  H01L2224/16135 ,  H01L2224/16268 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014

摘要： Provided is a method of manufacturing a semiconductor device including a bump interconnect structure. In the method of manufacturing the semiconductor device, a first substrate including a connection pad is formed, and a bump including a solder layer and a metal post protruding from the solder layer are formed on the connection pad. A second substrate including a bump land may be formed. The first substrate may be disposed on the second substrate so that a protruding end of the metal post contacts the bump land, and the solder layer may be reflowed. Accordingly, it possible to interconnect the metal post to the bump land.

公开(公告)号：US09947640B2

公开(公告)日：2018-04-17

申请号：US14287065

申请日：2014-05-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/16268 ,  H01L2224/32145 ,  H01L2224/32265 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/207 ,  H01L2924/00012

摘要： The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.

公开(公告)号：US20160035640A1

公开(公告)日：2016-02-04

申请号：US14782289

申请日：2014-03-27

申请人： NITTO DENKO CORPORATION

发明人： Kosuke MORITA ,  Naohide TAKAMOTO ,  Hiroyuki HANAZONO ,  Akihiro FUKUI

IPC分类号： H01L23/31 ,  C09J7/02 ,  H01L21/56

CPC分类号： H01L23/3157 ,  C09J7/38 ,  C09J2201/606 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/11002 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16238 ,  H01L2224/16268 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/05432 ,  H01L2924/207 ,  H01L2224/81 ,  H01L2224/83

摘要： The present invention provides an underfill film and a sealing sheet that are excellent in thermal conductive property and are capable of satisfactorily filling the space between the semiconductor element and the substrate. The present invention relates to an underfill film having a resin and a thermally conductive filler, in which a content of the thermally conductive filler is 50% by volume or more, an average particle size of the thermally conductive filler is 30% or less of a thickness of the underfill film, and a maximum particle size of the thermally conductive filler is 80% or less of the thickness of the underfill film.

摘要翻译： 本发明提供了导热性优异且能令人满意地填充半导体元件与基板之间的空间的底部填充膜和密封片。 本发明涉及一种具有树脂和导热性填料的底部填充膜，其中导热填料的含量为50体积％以上，导热性填料的平均粒径为30质量％以下 底部填充膜的厚度，导热性填料的最大粒径为底部填充膜的厚度的80％以下。

公开(公告)号：US20120018903A1

公开(公告)日：2012-01-26

申请号：US13186000

申请日：2011-07-19

申请人： Naohide TAKAMOTO ,  Goji SHIGA ,  Fumiteru ASAI

发明人： Naohide TAKAMOTO ,  Goji SHIGA ,  Fumiteru ASAI

IPC分类号： H01L23/48 ,  B32B3/00 ,  H01L21/50

CPC分类号： H01L21/6835 ,  C09J163/00 ,  H01L21/561 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16258 ,  H01L2224/16268 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/831 ,  H01L2224/83862 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/15788 ,  Y10T428/24802 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2224/13099

摘要： The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film having a light transmittance at a wavelength of 532 nm or 1064 nm of 20% or less, and having a contrast between a marking part and a part other than the marking part after laser marking of 20% or more.

摘要翻译： 本发明涉及一种用于倒装芯片型半导体背表面的薄膜，该薄膜形成在连接到被粘物上的半导体元件倒装芯片的背面上，该膜具有波长为532nm或1064nm的透光率为20 ％以下，并且在激光标记20％以上之后，标记部与标记部以外的部分之间具有对比度。

公开(公告)号：US20080030968A1

公开(公告)日：2008-02-07

申请号：US11882646

申请日：2007-08-03

申请人： Naohiro Mashino

发明人： Naohiro Mashino

IPC分类号： H05K7/02 ,  H01G13/00

CPC分类号： H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01G4/38 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2224/16268 ,  H01L2224/81192 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H05K1/162 ,  H05K2201/0367 ,  H05K2201/09763 ,  H05K2201/10378 ,  Y10T29/435

摘要： A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.

摘要翻译： 本发明的电容器内置插入件包括基底树脂层，设置成穿过基底树脂层并具有从基底树脂层的两个表面侧突出的突出部分的电容器第一电极，其中突出部分在一个 基础树脂层的表面侧用作连接部分，用于覆盖基础树脂层的另一表面侧上的第一电极的突出部分的电容器电介质层和用于覆盖电介质层的电容器第二电极，其中多个 每个由第一电极，电介质层和第二电极构成的电容器在电容器通过基础树脂层的状态下沿横向排列和排列。

公开(公告)号：US20180204825A1

公开(公告)日：2018-07-19

申请号：US15922932

申请日：2018-03-16

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： HuiLi FU ,  Song GAO

IPC分类号： H01L25/16 ,  H01G2/06 ,  H01L23/00

CPC分类号： H01L25/16 ,  H01G2/065 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16227 ,  H01L2224/16268 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.

公开(公告)号：US20160315061A1

公开(公告)日：2016-10-27

申请号：US15091122

申请日：2016-04-05

申请人： XINTEC INC.

发明人： Yen-Shih HO ,  Shu-Ming CHANG ,  Hsing-Lung SHEN

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L25/16

CPC分类号： H01L24/17 ,  H01L21/4846 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/08267 ,  H01L2224/08268 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16267 ,  H01L2224/16268 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/00014 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/11 ,  H01L2924/014

摘要： A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.

摘要翻译： 芯片封装包括第一芯片和第二芯片。 第一芯片包括具有第一表面和与第一表面相对的第二表面的第一基板，第一表面上的第一无源元件和覆盖第一无源元件的第一保护层，第一保护层具有第三表面 与第一个表面相对。 第一和第二导电焊盘结构设置在第一保护层中并电连接到第一无源元件。 第二芯片设置在第三表面上，第二芯片包括有源元件和与有源元件电连接的第二无源元件。 有源元件电连接到第一导电焊盘结构。

公开(公告)号：US08987830B2

公开(公告)日：2015-03-24

申请号：US12943673

申请日：2010-11-10

申请人： Shiann-Ming Liou ,  Albert Wu

发明人： Shiann-Ming Liou ,  Albert Wu

IPC分类号： H01L27/11 ,  H01L23/50 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/11 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/16 ,  H01L2224/11334 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16268 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19104 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了一种方法，包括在半导体管芯的表面上形成导电结构，将半导体管芯附接到基板，形成模制化合物以封装半导体管芯，在模制化合物中形成开口， 至少部分地暴露导电结构，并且通过模制化合物中的开口将无源部件电耦合到导电结构。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20100117782A1

公开(公告)日：2010-05-13

申请号：US12426589

申请日：2009-04-20

申请人： Hiroyuki SATO ,  Makoto NUMATA ,  Yo SAITO ,  Hitoshi TANAKA ,  Goro TAKEUCHI ,  Osamu TAGUCHI ,  Ryuichi TANAKA

发明人： Hiroyuki SATO ,  Makoto NUMATA ,  Yo SAITO ,  Hitoshi TANAKA ,  Goro TAKEUCHI ,  Osamu TAGUCHI ,  Ryuichi TANAKA

IPC分类号： H01C7/10

CPC分类号： H01C7/108 ,  H01C7/1006 ,  H01L23/62 ,  H01L23/647 ,  H01L33/641 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16268 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A varistor having a favorable heat-dissipating property is provided.In the varistor, a composite part having a favorable heat-dissipating property formed by a composite material composed of ZnO and Ag is arranged between main faces of a varistor matrix. Therefore, the heat transmitted from a semiconductor light-emitting device to a varistor part through an outer electrode can rapidly be transferred toward a main face on the opposite side through the composite part. In this varistor, side faces excluding inner side faces are exposed at side faces of the varistor matrix. Such a structure yields a favorable heat-dissipating property.

摘要翻译： 提供具有良好的散热特性的变阻器。 在变阻器中，通过由ZnO和Ag组成的复合材料形成的具有良好的散热特性的复合部件设置在压敏电阻矩阵的主面之间。 因此，通过外部电极从半导体发光元件传递到变阻器部分的热量可以快速地通过复合部件向相反侧的主面转移。 在该压敏电阻中，除了内侧面的侧面在压敏电阻矩阵的侧面露出。 这种结构产生良好的散热性能。

公开(公告)号：US20090011923A1

公开(公告)日：2009-01-08

申请号：US12204006

申请日：2008-09-04

申请人： Tomoyuki Hasegawa ,  Yoshinori Ide ,  Tadashi Otagiri

发明人： Tomoyuki Hasegawa ,  Yoshinori Ide ,  Tadashi Otagiri

IPC分类号： C04B35/468

CPC分类号： H05K1/162 ,  C04B35/4682 ,  C04B35/49 ,  C04B2235/3203 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3213 ,  C04B2235/3215 ,  C04B2235/3236 ,  C04B2235/3251 ,  C04B2235/3262 ,  C04B2235/3281 ,  C04B2235/3282 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/656 ,  C04B2235/77 ,  H01G4/1227 ,  H01G4/30 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16268 ,  H05K1/0306 ,  H05K3/4688 ,  H05K2201/0187

摘要： The present invention provides a dielectric porcelain composition comprising 100 parts by weight of a barium titanate-based dielectric material and 4 to 10 parts by weight in total of Bi2O3 and at least one compound selected from the group of consisting of CuO, ZnO and MgO.

摘要翻译： 本发明提供一种电介质瓷组合物，其包含100重量份的钛酸钡基电介质材料和4至10重量份的Bi 2 O 3和至少一种选自CuO，ZnO和MgO的化合物。