公开(公告)号：US20230178506A1

公开(公告)日：2023-06-08

申请号：US17917270

申请日：2020-06-05

Applicant: Mitsubishi Electric Corporation

Inventor： Tatsushi MORISADA

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/0603 ,  H01L2224/1131 ,  H01L2224/1369 ,  H01L2224/1624 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13551 ,  H01L2224/13566 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/32245

Abstract: A power semiconductor apparatus includes a conductive circuit pattern, a power semiconductor device, a sealing member, a conductive post, and a conductive post. A first conductive post is connected to the conductive circuit pattern. A second conductive post is connected to the power semiconductor device. The first conductive post includes a metal pin and a conductive bonding member. The conductive post includes a metal pin and a conductive bonding member.

公开(公告)号：US09881900B2

公开(公告)日：2018-01-30

申请号：US15379437

申请日：2016-12-14

Applicant: ROHM CO., LTD.

Inventor： Hirofumi Takeda ,  Yoshihisa Takada

IPC: H01L23/24 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0652 ,  G01C17/30 ,  H01L23/13 ,  H01L23/147 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11618 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13566 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/10158 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15321 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00012

Abstract: A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

公开(公告)号：US20170162535A1

公开(公告)日：2017-06-08

申请号：US14963037

申请日：2015-12-08

Applicant: Amkor Technology, Inc.

Inventor： Glenn Rinne

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/11422 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13624 ,  H01L2224/13647 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/16503 ,  H01L2224/16505 ,  H01L2224/16507 ,  H01L2224/8102 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01016 ,  H01L2924/01005

Abstract: A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.

公开(公告)号：US09379007B2

公开(公告)日：2016-06-28

申请号：US13874509

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charles L. Arvin ,  Kenneth Bird ,  Charles C. Goldsmith ,  Sung K. Kang ,  Minhua Lu ,  Clare J. McCarthy ,  Eric D. Perfecto ,  Srinivasa S. N. Reddy ,  Krystyna W. Semkow ,  Thomas A. Wassick

IPC: H01L21/321 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/7685 ,  H01L21/321 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0382 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1111 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/181 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

Abstract translation: 本发明的实施例包括无铅焊料互连结构和用于制造无铅互连结构的方法。 该结构包括具有最后金属层的半导体衬底，附着于最后金属层的铜基座，附着于铜基座的阻挡层，与阻挡层连接的阻挡保护层，以及与该阻挡层相接触的无铅焊料层 铜底座的最小一侧。

公开(公告)号：US20150380371A1

公开(公告)日：2015-12-31

申请号：US14844268

申请日：2015-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei Sen CHANG

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/01051 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming an integrated circuit device includes forming a mask layer overlying an under bump metallurgy (UBM) layer, wherein the mask layer comprises a first portion adjacent to the UBM layer, and a second portion overlying the first portion. The method further includes forming an opening in the mask layer to expose a portion of the UBM layer. The method further includes forming a conductive layer in the opening of the mask layer, electrically connected to the exposed portion of the UBM layer. The method further includes removing the second portion of the mask layer to expose an upper portion of the conductive layer. The method further includes forming a barrier layer on the exposed upper portion of the conductive layer.

Abstract translation: 形成集成电路器件的方法包括形成覆盖凸块下的冶金（UBM）层的掩模层，其中掩模层包括与UBM层相邻的第一部分和覆盖第一部分的第二部分。 该方法还包括在掩模层中形成开口以暴露UBM层的一部分。 该方法还包括在掩模层的开口中形成导电层，电连接到UBM层的暴露部分。 该方法还包括去除掩模层的第二部分以暴露导电层的上部。 该方法还包括在导电层的暴露的上部形成阻挡层。

公开(公告)号：US09219016B2

公开(公告)日：2015-12-22

申请号：US13247659

申请日：2011-09-28

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H05K7/00 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L22/32 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/13578 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A work piece includes a first copper-containing pillar having a top surface and sidewalls, and a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar. A test pad includes a second copper-containing pillar having a top surface and sidewalls. The test pad is electrically coupled to the first copper-containing pillar. A second protection layer is disposed on the sidewalls, and not over the top surface, of the second copper-containing pillar. The first and the second protection layers include a compound of copper and a polymer, and are dielectric layers.

Abstract translation: 工件包括具有顶表面和侧壁的第一含铜柱，以及第一含铜柱的侧壁而不是顶表面上的第一保护层。 测试垫包括具有顶表面和侧壁的第二含铜柱。 测试垫电耦合到第一含铜柱。 第二保护层设置在第二含铜柱的侧壁上，而不是在顶表面上。 第一和第二保护层包括铜和聚合物的化合物，并且是电介质层。

公开(公告)号：US20130249066A1

公开(公告)日：2013-09-26

申请号：US13427940

申请日：2012-03-23

Applicant: CHARLES L. ARVIN ,  KENNETH BIRD ,  CHARLES C. GOLDSMITH ,  SUNG K. KANG ,  MINHUA LU ,  CLARE JOHANNA MCCARTHY ,  ERIC DANIEL PERFECTO ,  SRINIVASA S.N. REDDY ,  KRYSTYNA WALERIA SEMKOW ,  THOMAS ANTHONY WASSICK

Inventor： CHARLES L. ARVIN ,  KENNETH BIRD ,  CHARLES C. GOLDSMITH ,  SUNG K. KANG ,  MINHUA LU ,  CLARE JOHANNA MCCARTHY ,  ERIC DANIEL PERFECTO ,  SRINIVASA S.N. REDDY ,  KRYSTYNA WALERIA SEMKOW ,  THOMAS ANTHONY WASSICK

IPC: H01L23/495 ,  H01L21/28

CPC classification number: H01L21/7685 ,  H01L21/321 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0382 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1111 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/181 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

公开(公告)号：US20130175698A1

公开(公告)日：2013-07-11

申请号：US13345422

申请日：2012-01-06

Applicant: Jaspreet S. Gandhi ,  Brandon P. Wirz ,  Yangyang Sun ,  Josh D. Woodland

Inventor： Jaspreet S. Gandhi ,  Brandon P. Wirz ,  Yangyang Sun ,  Josh D. Woodland

IPC: H01L23/48 ,  H01L21/30

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L23/293 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11822 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/14131 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81862 ,  H01L2224/81905 ,  H01L2224/81907 ,  H01L2224/83104 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/05552

Abstract: An integrated circuit construction includes a stack of two or more integrated circuit substrates. At least one of the substrates includes through substrate vias (TSVs) individually comprising opposing ends. A conductive bond pad is adjacent one of the ends on one side of the one substrate. A conductive solder mass is adjacent the other end projecting elevationally on the other side of the one substrate. Individual of the solder masses are bonded to a respective bond pad on an immediately adjacent substrate of the stack. Epoxy flux surrounds the individual solder masses. An epoxy material different in composition from the epoxy flux surrounds the epoxy flux on the individual solder masses. Methods of forming integrated circuit constructions are also disclosed.

Abstract translation: 集成电路结构包括两个或多个集成电路基板的堆叠。 衬底中的至少一个包括单独包括相对端的通过衬底通孔（TSV）。 导电接合焊盘与一个衬底的一侧上的一个端部相邻。 导电焊料块在另一端相邻，另一端在一个衬底的另一侧向上突出突出。 焊料块的单个结合到堆叠的紧邻衬底上的相应接合焊盘。 环氧助焊剂包围各个焊料块。 与环氧树脂焊剂组成不同的环氧树脂材料围绕单个焊料块上的环氧树脂焊剂。 还公开了形成集成电路结构的方法。

公开(公告)号：US20130099359A1

公开(公告)日：2013-04-25

申请号：US13565396

申请日：2012-08-02

Applicant: Sung Min KIM

Inventor： Sung Min KIM

IPC: H01L23/488 ,  H01L25/07

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/1161 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13186 ,  H01L2224/1319 ,  H01L2224/13566 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/14181 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16147 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/114 ,  H01L2224/1182

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

Abstract translation: 半导体封装包括具有多个接合焊盘的半导体芯片，以半导体芯片形成的电介质构件，以暴露各个焊盘的部分并具有梯形截面形状，并且形成为覆盖露出部分的凸块 各个接合焊盘和电介质部件的一部分，并具有阶梯状截面形状。

公开(公告)号：US20130087906A1

公开(公告)日：2013-04-11

申请号：US13253088

申请日：2011-10-05

Applicant: Pai-Sheng Cheng ,  Chia-Hui Wu

Inventor： Pai-Sheng Cheng ,  Chia-Hui Wu

IPC: H01L23/498

CPC classification number: H01L24/11 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13624 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16058 ,  H01L2224/16502 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/8185 ,  H01L2224/83193 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a circuit board including a substrate, at least one lead, at least one bump, and a solder layer. The lead is disposed on the substrate, and the bump is disposed on the lead. The solder layer covers the lead and the bump.

Abstract translation: 本发明提供一种电路板，其包括基板，至少一个引线，至少一个凸块和焊料层。 引线设置在基板上，并且凸块设置在引线上。 焊料层覆盖引线和凸块。