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    Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor
    1.
    发明授权
    Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor 有权
    采用激光辅助化学气相沉积导体的通孔的硅芯片载体

    公开(公告)号：US07019402B2

    公开(公告)日：2006-03-28

    申请号：US10686640

    申请日：2003-10-17

    Applicant: Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Russell Alan Budd ,  Thomas Anthony Wassick

    Inventor： Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Russell Alan Budd ,  Thomas Anthony Wassick

    IPC: H01L23/48

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.

    Abstract translation: 该公开内容教导了使用金属的激光辅助化学气相沉积在硅或玻璃基板中填充深通孔或者封装深导电糊填充通孔的方法。 该方法使用连续波或脉冲激光器通过选择激光波长来选择性地加热通孔底部和生长金属填充物，使得硅和/或玻璃不以任何可察觉的方式吸收激光的能量以在场中沉积 。 或者，可以使用全息掩模或微透镜阵列来将激光束聚焦到通孔以用金属填充它们。 以大约的沉积速率，以z方向以受控方式远离激光器移动衬底，从而使激光加热聚焦在生长金属填充物的表面区域上。

    Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
    4.
    发明授权
    Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners 失效
    具有裂纹停止区域的半导体芯片，用于减少从芯片边缘/角落的裂纹扩展

    公开(公告)号：US07732932B2

    公开(公告)日：2010-06-08

    申请号：US11833348

    申请日：2007-08-03

    Applicant: Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    Inventor： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    IPC: H01L23/492

    CPC classification number: H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

    Abstract: Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

    Abstract translation: 结构及其形成方法。 该结构包括半导体衬底，半导体衬底上的晶体管和半导体衬底顶部的N个互连层，N为正整数。 晶体管电耦合到N个互连层。 该结构还包括在N个互连层的顶部上的第一介电层和在第一介电层的顶部上的P个裂纹停止区，P是正整数。 该结构还包括在第一电介质层的顶部上的第二电介质层。 P裂纹停止区域的每个裂纹停止区域被第一介电层和第二介电层完全包围。 该结构还包括在第二电介质层的顶部上的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。

    SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS
    7.
    发明申请
    SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS 失效
    带切割停止区域的半导体焊盘，用于减少芯片边缘/角落的裂纹传播

    公开(公告)号：US20090032909A1

    公开(公告)日：2009-02-05

    申请号：US11833348

    申请日：2007-08-03

    Applicant: Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    Inventor： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    IPC: H01L23/58 ,  H01L21/64

    CPC classification number: H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

    Abstract: Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

    Abstract translation: 结构及其形成方法。 该结构包括半导体衬底，半导体衬底上的晶体管和半导体衬底顶部的N个互连层，N为正整数。 晶体管电耦合到N个互连层。 该结构还包括在N个互连层的顶部上的第一介电层和在第一介电层的顶部上的P个裂纹停止区，P是正整数。 该结构还包括在第一电介质层的顶部上的第二电介质层。 P裂纹停止区域的每个裂纹停止区域被第一介电层和第二介电层完全包围。 该结构还包括在第二电介质层的顶部上的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。

    Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
    9.
    发明授权
    Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners 有权
    具有裂纹停止区域的半导体芯片，用于减少从芯片边缘/角落的裂纹扩展

    公开(公告)号：US07875502B2

    公开(公告)日：2011-01-25

    申请号：US12788521

    申请日：2010-05-27

    Applicant: Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    Inventor： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    IPC: H01L21/78

    CPC classification number: H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

    Abstract: A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.

    Abstract translation: 芯片制造方法。 提供的结构包括：半导体衬底上的晶体管，半导体衬底上的N个互连层和晶体管（N> 0），以及N个互连层上的第一介电层。 晶体管电耦合到N个互连层。 在第一介电层（P，Q> 0）上形成有P断裂区域和Q裂纹停止区域。 第一电介质层夹在N互连层和形成在第一介电层上的第二电介质层之间。 每个P裂纹停止区域被第一和第二介电层完全包围。 第二电介质层夹在第一电介质层和形成在第二电介质层上的底部填充层之间。 每个Q裂纹停止区域被第一介电层和底部填充层完全包围。

    SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS
    10.
    发明申请
    SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS 有权
    带切割停止区域的半导体焊盘，用于减少芯片边缘/角落的裂纹传播

    公开(公告)号：US20100233872A1

    公开(公告)日：2010-09-16

    申请号：US12788521

    申请日：2010-05-27

    Applicant: Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    Inventor： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    IPC: H01L21/71

    CPC classification number: H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

    Abstract: A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.

    Abstract translation: 芯片制造方法。 提供的结构包括：半导体衬底上的晶体管，半导体衬底上的N个互连层和晶体管（N> 0），以及N个互连层上的第一介电层。 晶体管电耦合到N个互连层。 在第一介电层（P，Q> 0）上形成有P断裂区域和Q裂纹停止区域。 第一电介质层夹在N互连层和形成在第一介电层上的第二电介质层之间。 每个P裂纹停止区域被第一和第二介电层完全包围。 第二电介质层夹在第一电介质层和形成在第二电介质层上的底部填充层之间。 每个Q裂纹停止区域被第一介电层和底部填充层完全包围。

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