公开(公告)号：US10157872B2

公开(公告)日：2018-12-18

申请号：US16035231

申请日：2018-07-13

Applicant: Amkor Technology, Inc.

Inventor： Greg Hames ,  Glenn Rinne ,  Devarajan Balaraman

IPC: H01L21/44 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

公开(公告)号：US10056349B2

公开(公告)日：2018-08-21

申请号：US15831771

申请日：2017-12-05

Applicant: Amkor Technology, Inc.

Inventor： Yeong Beom Ko ,  Jin Han Kim ,  Dong Jin Kim ,  Do Hyung Kim ,  Glenn Rinne

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/48 ,  H01L21/311 ,  H01L25/00 ,  H01L25/065 ,  H01L21/78 ,  H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/96 ,  H01L21/311 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/014

Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.

公开(公告)号：US20180138138A1

公开(公告)日：2018-05-17

申请号：US15350647

申请日：2016-11-14

Applicant: Amkor Technology, Inc.

Inventor： Greg Hames ,  Glenn Rinne ,  Devarajan Balaraman

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/11462 ,  H01L2224/11614 ,  H01L2224/13026

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

公开(公告)号：US09875980B2

公开(公告)日：2018-01-23

申请号：US14286263

申请日：2014-05-23

Applicant: Amkor Technology, Inc.

Inventor： Glenn Rinne ,  Dean Zehnder ,  Christopher J. Berry ,  Robert Lanzone ,  Ludovico Bancod

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05567 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83192 ,  H01L2924/15311 ,  H01L2924/3651 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods for copper pillar protection may include forming a metal post over a contact on a semiconductor die, where the metal post comprises a sidewall. A metal cap may be formed on the metal post and may be wider than the width of the metal post. A solder bump may be formed on the metal cap, and a conformal passivation layer may be formed on at least the sidewall of the metal post. The metal cap may be rounded shaped or rectangular shaped in cross-section. The metal post and the metal cap may comprise copper. The metal cap may comprise a copper layer and a nickel layer. The seed metal layer may comprise one or more of titanium, tungsten, and copper. The conformal passivation layer may comprise a nonwettable polymer. Horizontal portions of the conformal passivation layer may be removed utilizing an anisotropic etch such as a plasma etch.

公开(公告)号：US20150041975A1

公开(公告)日：2015-02-12

申请号：US14456226

申请日：2014-08-11

Applicant: Amkor Technology, Inc.

Inventor： Ji Young Chung ,  Choon Heung Lee ,  Glenn Rinne ,  Byong Jin Kim

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/19107 ,  H01L2924/00014

Abstract: A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package comprising a mounting board. At least one second semiconductor die may be mounted on the mounting board, and one or more leads may be electrically connected to the mounting board and/or the second semiconductor die. An adhesion member may bond the first package to the second package, and an encapsulant may encapsulate the first package and the second package. the circuit board, the mounting board, and the one or more leads may be arranged to surround the first semiconductor die and the second semiconductor die, and the plurality of leads may be electrically connected to the circuit board and to a constant potential or ground, to reduce the effects of external electromagnetic interference upon the semiconductor package.

Abstract translation: 半导体封装包括第一封装，包括电路板和安置在电路板上的第一半导体管芯，第二封装包括安装板。 至少一个第二半导体管芯可以安装在安装板上，并且一个或多个引线可以电连接到安装板和/或第二半导体管芯。 粘合构件可以将第一包装物粘合到第二包装，并且密封剂可以封装第一包装和第二包装。 电路板，安装板和一个或多个引线可以布置成围绕第一半导体管芯和第二半导体管芯，并且多个引线可以电连接到电路板和恒定电位或接地， 以减少外部电磁干扰对半导体封装的影响。

公开(公告)号：US10832921B2

公开(公告)日：2020-11-10

申请号：US16424046

申请日：2019-05-28

Applicant: Amkor Technology, Inc.

Inventor： Devarajan Balaraman ,  Daniel Richter ,  Greg Hames ,  Dean Zehnder ,  Glenn Rinne

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L21/683

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

公开(公告)号：US20180102342A1

公开(公告)日：2018-04-12

申请号：US15831771

申请日：2017-12-05

Applicant: Amkor Technology, Inc.

Inventor： Yeong Beom Ko ,  Jin Han Kim ,  Dong Jin Kim ,  Do Hyung Kim ,  Glenn Rinne

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/311

CPC classification number: H01L24/96 ,  H01L21/311 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/014

Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.

公开(公告)号：US20180047692A1

公开(公告)日：2018-02-15

申请号：US15233271

申请日：2016-08-10

Applicant: Amkor Technology, Inc.

Inventor： Glenn Rinne ,  Daniel Richter

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/06051 ,  H01L2224/06177 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14141 ,  H01L2224/14151 ,  H01L2224/14153 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/81815 ,  H01L2924/10156 ,  H01L2924/15311 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

公开(公告)号：US20170162535A1

公开(公告)日：2017-06-08

申请号：US14963037

申请日：2015-12-08

Applicant: Amkor Technology, Inc.

Inventor： Glenn Rinne

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/11422 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13624 ,  H01L2224/13647 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/16503 ,  H01L2224/16505 ,  H01L2224/16507 ,  H01L2224/8102 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01016 ,  H01L2924/01005

Abstract: A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.

公开(公告)号：US09406639B2

公开(公告)日：2016-08-02

申请号：US13962735

申请日：2013-08-08

Applicant: Amkor Technology, Inc.

Inventor： Jin Young Kim ,  No Sun Park ,  Yoon Joo Kim ,  Choon Heung Lee ,  Jin Han Kim ,  Seung Jae Lee ,  Se Woong Cha ,  Sung Kyu Kim ,  Glenn Rinne

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/00

Abstract: A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.

Abstract translation: 公开了半导体封装及其制造方法，并且可以包括第一半导体器件，其包括在第一半导体器件的第一表面上的第一接合焊盘，围绕第一半导体器件的侧边缘的第一密封剂材料和再分配层（RDL ）形成在第一半导体器件的第一表面上并且在密封剂材料的第一表面上。 RDL可以将第一接合焊盘电耦合到形成在密封剂材料的第一表面上方的第二接合焊盘。 包括在第二半导体器件的第一表面上的第三接合焊盘的第二半导体器件可面向第一半导体器件的第一表面并且电耦合到第一半导体器件上的第一接合焊盘。 第一半导体器件的第一表面可以与密封剂材料的第一表面共面。