公开(公告)号：US09030001B2

公开(公告)日：2015-05-12

申请号：US14058955

申请日：2013-10-21

Applicant: Tessera, Inc.

Inventor： Belgacem Haba

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L21/50 ,  B82Y40/00

CPC classification number: H01L24/17 ,  B82Y40/00 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/49811 ,  H01L23/52 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/116 ,  H01L2224/1182 ,  H01L2224/11821 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13794 ,  H01L2224/13911 ,  H01L2224/13944 ,  H01L2224/13947 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/81026 ,  H01L2224/81099 ,  H01L2224/81143 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  Y10S977/773 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof.

Abstract translation: 制造组件的方法包括以下步骤：将金属纳米颗粒施加到第一部件和第二部件中的任一个或两者的导电元件的暴露表面上，将第一部件的导电元件与第二部件的导电元件并置， 设置在其间的金属纳米颗粒，并且至少在并置的导电元件的界面处将温度升高到金属纳米粒子在并置的导电元件之间形成冶金接合部的接合温度。 第一部件和第二部件中的任一个或两者的导电元件可以包括基本上刚性的支柱，其具有突出在相应部件的表面上方的高度的顶表面，并且远离其顶表面以基本角度延伸的边缘表面。

公开(公告)号：US20140117523A1

公开(公告)日：2014-05-01

申请号：US13663694

申请日：2012-10-30

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/4952 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2221/68327 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/13794 ,  H01L2224/13839 ,  H01L2224/1403 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40248 ,  H01L2224/40499 ,  H01L2224/405 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/00012

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract translation: 本发明涉及一种功率半导体器件及其制备方法，特别涉及使用具有两个互连板的倒装芯片技术来制备MOSFET（金属氧化物半导体场效应晶体管）的层叠双芯片封装结构。 第一芯片被翻转并附接在基座上，使得第一芯片与第三引脚重叠; 第一芯片的背金属层通过第一互连板连接到第一引脚的接合条; 第二芯片被翻转并附接在第一互连板的主板部分上，使得第二芯片与第四引脚重叠; 并且第二芯片的背金属层通过第二互连板连接到第二引脚的接合条。

公开(公告)号：US20120286423A1

公开(公告)日：2012-11-15

申请号：US13556016

申请日：2012-07-23

Applicant: Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

Inventor： Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

IPC: H01L23/498

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11416 ,  H01L2224/11422 ,  H01L2224/11424 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/11827 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/132 ,  H01L2224/13211 ,  H01L2224/13339 ,  H01L2224/13562 ,  H01L2224/13584 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/1379 ,  H01L2224/13794 ,  H01L2224/13809 ,  H01L2224/13813 ,  H01L2224/13817 ,  H01L2224/13818 ,  H01L2224/1382 ,  H01L2224/13849 ,  H01L2224/13855 ,  H01L2224/13857 ,  H01L2224/1386 ,  H01L2224/13866 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/93 ,  H01L2225/06513 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

公开(公告)号：US09293432B2

公开(公告)日：2016-03-22

申请号：US14441477

申请日：2013-10-30

Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.

Inventor： Chang-Ming Lin ,  Lei Shi ,  Haijun Shen

IPC: H01L23/48 ,  H01L21/00 ,  B23K31/02 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13599 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13794 ,  H01L2224/138 ,  H01L2224/13811 ,  H01L2224/81191 ,  H01L2924/01028 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/35 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging.

Abstract translation: 一种芯片封装结构和封装方法。 包装结构包括：半导体衬底; 设置在所述半导体衬底内的金属焊盘; 绝缘层，设置在所述半导体衬底上，所述绝缘层具有用于暴露所述金属焊盘的开口; 设置在金属垫上的子球金属电极; 设置在所述子球金属电极的表面上的焊球，所述焊球具有第一挡板结构，所述第一挡板结构覆盖所述球下金属电极的底部周边的部分金属焊盘。 本发明的芯片封装结构增强了焊锡球与金属焊盘之间的粘合性，提高了芯片封装的可靠性。

公开(公告)号：US09184117B2

公开(公告)日：2015-11-10

申请号：US13663694

申请日：2012-10-30

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L29/40 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L23/4952 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2221/68327 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/13794 ,  H01L2224/13839 ,  H01L2224/1403 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40248 ,  H01L2224/40499 ,  H01L2224/405 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/00012

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract translation: 本发明涉及一种功率半导体器件及其制备方法，特别涉及使用具有两个互连板的倒装芯片技术来制备MOSFET（金属氧化物半导体场效应晶体管）的层叠双芯片封装结构。 第一芯片被翻转并附接在基座上，使得第一芯片与第三引脚重叠; 第一芯片的背金属层通过第一互连板连接到第一引脚的接合条; 第二芯片被翻转并附接在第一互连板的主板部分上，使得第二芯片与第四引脚重叠; 并且第二芯片的背金属层通过第二互连板连接到第二引脚的接合条。

公开(公告)号：US20150294949A1

公开(公告)日：2015-10-15

申请号：US14441477

申请日：2013-10-30

Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.

Inventor： Chang-Ming Lin ,  Lei Shi ,  Haijun Shen

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13599 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13794 ,  H01L2224/138 ,  H01L2224/13811 ,  H01L2224/81191 ,  H01L2924/01028 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/35 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging.

Abstract translation: 一种芯片封装结构和封装方法。 包装结构包括：半导体衬底; 设置在所述半导体衬底内的金属焊盘; 绝缘层，设置在所述半导体衬底上，所述绝缘层具有用于暴露所述金属焊盘的开口; 设置在金属垫上的子球金属电极; 设置在所述子球金属电极的表面上的焊球，所述焊球具有第一挡板结构，所述第一挡板结构覆盖所述球下金属电极的底部周边的部分金属焊盘。 本发明的芯片封装结构增强了焊锡球与金属焊盘之间的粘合性，提高了芯片封装的可靠性。

公开(公告)号：US20150243624A1

公开(公告)日：2015-08-27

申请号：US14707465

申请日：2015-05-08

Applicant: Tessera, Inc.

Inventor： Belgacem Haba

IPC: H01L23/00

CPC classification number: H01L24/17 ,  B82Y40/00 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/49811 ,  H01L23/52 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/116 ,  H01L2224/1182 ,  H01L2224/11821 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13794 ,  H01L2224/13911 ,  H01L2224/13944 ,  H01L2224/13947 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/81026 ,  H01L2224/81099 ,  H01L2224/81143 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  Y10S977/773 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof.

Abstract translation: 制造组件的方法包括以下步骤：将金属纳米颗粒施加到第一部件和第二部件中的任一个或两者的导电元件的暴露表面上，将第一部件的导电元件与第二部件的导电元件并置， 设置在其间的金属纳米颗粒，并且至少在并置的导电元件的界面处将温度升高到金属纳米粒子在并置的导电元件之间形成冶金接头的接合温度。 第一部件和第二部件中的任一个或两者的导电元件可以包括基本上刚性的支柱，其具有突出在相应部件的表面上方的高度的顶表面，并且远离其顶表面以基本角度延伸的边缘表面。

公开(公告)号：US20140077351A1

公开(公告)日：2014-03-20

申请号：US14058955

申请日：2013-10-21

Applicant: Tessera, Inc.

Inventor： Belgacem Haba

IPC: H01L23/52 ,  H01L21/50

CPC classification number: H01L24/17 ,  B82Y40/00 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/49811 ,  H01L23/52 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/116 ,  H01L2224/1182 ,  H01L2224/11821 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13794 ,  H01L2224/13911 ,  H01L2224/13944 ,  H01L2224/13947 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/81026 ,  H01L2224/81099 ,  H01L2224/81143 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  Y10S977/773 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof.

Abstract translation: 制造组件的方法包括以下步骤：将金属纳米颗粒施加到第一部件和第二部件中的任一个或两者的导电元件的暴露表面上，将第一部件的导电元件与第二部件的导电元件并置， 置于其间的金属纳米颗粒，并且至少在并置的导电元件的界面处将温度升高到金属纳米粒子在并置的导电元件之间形成冶金接头的接合温度。 第一部件和第二部件中的任一个或两者的导电元件可以包括基本上刚性的支柱，其具有突出在相应部件的表面上方的高度的顶表面，并且远离其顶表面以基本角度延伸的边缘表面。

公开(公告)号：US20120025365A1

公开(公告)日：2012-02-02

申请号：US12844463

申请日：2010-07-27

Applicant: Belgacem Haba

Inventor： Belgacem Haba

IPC: H01L25/00 ,  H01L23/52 ,  H01L21/50

CPC classification number: H01L24/17 ,  B82Y40/00 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/49811 ,  H01L23/52 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/116 ,  H01L2224/1182 ,  H01L2224/11821 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13794 ,  H01L2224/13911 ,  H01L2224/13944 ,  H01L2224/13947 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/81026 ,  H01L2224/81099 ,  H01L2224/81143 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  Y10S977/773 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof.

Abstract translation: 制造组件的方法包括以下步骤：将金属纳米颗粒施加到第一部件和第二部件中的任一个或两者的导电元件的暴露表面上，将第一部件的导电元件与第二部件的导电元件并置， 设置在其间的金属纳米颗粒，并且至少在并置的导电元件的界面处将温度升高到金属纳米粒子在并置的导电元件之间形成冶金接头的接合温度。 第一部件和第二部件中的任一个或两者的导电元件可以包括基本上刚性的支柱，其具有突出在相应部件的表面上方的高度的顶表面，并且远离其顶表面以基本角度延伸的边缘表面。

公开(公告)号：US20120018878A1

公开(公告)日：2012-01-26

申请号：US12843760

申请日：2010-07-26

Applicant: Ming-Da Cheng ,  MIng-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

Inventor： Ming-Da Cheng ,  MIng-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

IPC: H01L21/288 ,  H01L29/45

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11416 ,  H01L2224/11422 ,  H01L2224/11424 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/11827 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/132 ,  H01L2224/13211 ,  H01L2224/13339 ,  H01L2224/13562 ,  H01L2224/13584 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/1379 ,  H01L2224/13794 ,  H01L2224/13809 ,  H01L2224/13813 ,  H01L2224/13817 ,  H01L2224/13818 ,  H01L2224/1382 ,  H01L2224/13849 ,  H01L2224/13855 ,  H01L2224/13857 ,  H01L2224/1386 ,  H01L2224/13866 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/93 ,  H01L2225/06513 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Abstract translation: 形成器件的方法包括提供衬底，以及在衬底上形成焊料凸点。 将次要元件引入邻近焊料凸块顶表面的区域。 然后对焊料凸块执行再流程以将次要元件驱动到焊料凸块中。