公开(公告)号：US12033974B2

公开(公告)日：2024-07-09

申请号：US17512860

申请日：2021-10-28

Applicant: Shanghai Tianma Micro-Electronics Co., Ltd.

Inventor： Quanpeng Yu

IPC: H01L23/00 ,  H01L25/075 ,  H01L25/16

CPC classification number: H01L24/83 ,  H01L24/32 ,  H01L24/33 ,  H01L24/93 ,  H01L25/0753 ,  H01L25/162 ,  H01L25/167 ,  H01L24/29 ,  H01L24/30 ,  H01L2224/26122 ,  H01L2224/26152 ,  H01L2224/29012 ,  H01L2224/30155 ,  H01L2224/32137 ,  H01L2224/32221 ,  H01L2224/33164 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83951

Abstract: Provided are a display panel, a preparation method thereof, and a display device. The display panel includes a plurality of sub-panels. Each sub-panel includes first substrate, second substrate, bezel adhesive located therebetween, a plurality of bank structures, and a plurality of light-emitting elements. At least one light-emitting element forms a pixel unit. Each bank structure is located between adjacent pixel units. Seaming adhesive is located between adjacent sub-panels. The sub-panels share a same first substrate, and the seaming adhesive is disposed on the same first substrate. The first substrate includes a display region and a non-display region surrounding the display region. The light-emitting elements and the bank structures are located in the display region, and the bezel adhesive is located in the non-display region. In this manner, splicing gaps between adjacent sub-panels can be effectively reduced, and thus the display effect of the display panel can be improved.

公开(公告)号：US20240136333A1

公开(公告)日：2024-04-25

申请号：US18535375

申请日：2023-12-11

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Rajesh Katkar ,  Belgacem Haba

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/06 ,  H01L24/26 ,  H01L24/93

Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.

公开(公告)号：US11798905B2

公开(公告)日：2023-10-24

申请号：US17488053

申请日：2021-09-28

Applicant: LAPIS Semiconductor Co., Ltd.

Inventor： Takashi Shimada

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/93 ,  H01L2224/022 ,  H01L2224/03001 ,  H01L2224/03602 ,  H01L2224/05005

Abstract: The semiconductor device according to the present invention comprises; a semiconductor element having one surface with a plurality of electrode pads; an electrode structure including a plurality of metal terminals and a sealing resin. The plurality of metal terminals being disposed in a region along a circumference of the one surface. The sealing resin holding the plurality of metal terminals and being disposed on the one surface of the semiconductor element. The electrode structure includes a first surface opposed to the one surface of the semiconductor element, a second surface positioned in an opposite side of the first surface, and a third surface positioned between the first surface and the second surface. Each of the plurality of metal terminals is exposed from the sealing resin in at least a part of the second surface and at least a part of the third surface.

公开(公告)号：US09894771B2

公开(公告)日：2018-02-13

申请号：US13228826

申请日：2011-09-09

Applicant: Joseph Charles Fjelstad

Inventor： Joseph Charles Fjelstad

IPC: B32B37/10 ,  B32B37/12 ,  B32B37/02 ,  B32B37/14 ,  H05K1/18 ,  B32B37/15 ,  H01L23/00 ,  H01L25/065 ,  H05K3/28 ,  H05K3/00

CPC classification number: H05K1/189 ,  B32B37/12 ,  B32B37/153 ,  B32B2307/202 ,  B32B2457/08 ,  B32B2519/02 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L25/0655 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/48465 ,  H01L2224/83001 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/3025 ,  H05K3/007 ,  H05K3/284 ,  H05K2201/066 ,  H05K2201/10719 ,  H05K2203/0156 ,  H05K2203/0173 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199

Abstract: An Occam process (solderless manufacturing) that employs a component support fixture that provides permanent or temporary support for components during subsequent processing in a solderless process for electrically connecting the components to circuits. The component support fixture provides oversized compartments for housing the components which may have varying sizes. The compartments are provided with vent holes or apertures for venting air or excess glue as the component support is pressed against the components during manufacture.

公开(公告)号：US09771259B2

公开(公告)日：2017-09-26

申请号：US14932814

申请日：2015-11-04

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: B81C1/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: B81C1/00325 ,  B81B2207/092 ,  B81B2207/097 ,  B81C1/00301 ,  B81C2201/0115 ,  B81C2203/0118 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L2221/68304 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2221/68386 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15788 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

公开(公告)号：US20150364434A1

公开(公告)日：2015-12-17

申请号：US14302666

申请日：2014-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L21/3081 ,  H01L21/764 ,  H01L23/498 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/83 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03845 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0601 ,  H01L2224/08147 ,  H01L2224/0901 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes a diffusion barrier layer that includes sidewall portions, and a metallic material encircled by the sidewall portions of the diffusion barrier layer. The metallic material has a second planar surface level with the first planar surface. An air gap extends from the second planar surface of the metallic material into the metallic material. An edge of the air gap is aligned to an edge of the metallic material.

Abstract translation: 封装部件包括具有第一平坦表面的表面电介质层和表面电介质层中的金属焊盘。 金属焊盘包括包括侧壁部分的扩散阻挡层和由扩散阻挡层的侧壁部分包围的金属材料。 金属材料具有与第一平坦表面的第二平面表面水平。 气隙从金属材料的第二平面延伸到金属材料中。 气隙的边缘与金属材料的边缘对准。

公开(公告)号：US20140329361A1

公开(公告)日：2014-11-06

申请号：US14335660

申请日：2014-07-18

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Konrad Roesl ,  Oliver Eichinger

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/3107 ,  H01L23/49513 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/93 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/27426 ,  H01L2224/2745 ,  H01L2224/29018 ,  H01L2224/29019 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/8381 ,  H01L2224/83898 ,  H01L2224/83906 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2224/27 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.

Abstract translation: 一种方法包括提供具有沉积在第一主表面上的第一主表面和焊料层的半导体芯片，其中焊料层的粗糙度至少为1μm。 将半导体芯片放置在载体上，半导体芯片的第一主表面面向载体。 将半导体芯片按第一主表面的表面积至少为1牛顿/千克的压力压在载体上，并将热量施加到焊料材料上。

公开(公告)号：US08835940B2

公开(公告)日：2014-09-16

申请号：US13625825

申请日：2012-09-24

Applicant: Hsin-Hua Hu ,  Andreas Bibl ,  John A. Higginson

Inventor： Hsin-Hua Hu ,  Andreas Bibl ,  John A. Higginson

IPC: H01L33/48

CPC classification number: H01L21/52 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/83 ,  H01L24/93 ,  H01L24/95 ,  H01L25/0753 ,  H01L25/50 ,  H01L27/156 ,  H01L33/0079 ,  H01L33/40 ,  H01L2221/6835 ,  H01L2224/95136 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Abstract translation: 公开了一种稳定微器件阵列的方法和结构。 微器件阵列形成在由热固性材料形成的稳定柱阵列上。 每个微型装置包括比直接在底面下面的相应稳定柱更宽的底表面。

公开(公告)号：US08802564B2

公开(公告)日：2014-08-12

申请号：US13460939

申请日：2012-05-01

Applicant: Mathias Kock ,  Ronald Eisele

Inventor： Mathias Kock ,  Ronald Eisele

IPC: H01L21/44

CPC classification number: H01L21/568 ,  C23C4/01 ,  C23C4/02 ,  C23C4/134 ,  C23C4/18 ,  H01L21/561 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/05 ,  H01L24/93 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/03418 ,  H01L2224/03442 ,  H01L2224/03444 ,  H01L2224/056 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/00014 ,  H01L2224/03

Abstract: A method of manufacturing a semiconductor component includes the steps of manufacturing of a wafer, applying structures of components on the wafer to form a wafer assembly, applying a metal coating on the wafer, removing the metal coating in non-contact areas of the components, applying surrounds on the edge areas of the components, arranging the wafer on a foil held by a clamping ring, separating the components of the wafer compound carried by the foil from one another, arranging a covering mask on the areas of the separated components carried by the foil which are not to be coated, applying a metal coating on the separate components covered with the mask, removal of the mask, and removal of the components from the foil and further processing the separate components wherein that applying a metal coating on the separate components covered by the mask takes place by means of thermal spraying.

Abstract translation: 制造半导体部件的方法包括以下步骤：制造晶片，在晶片上施加部件结构以形成晶片组件，在晶片上施加金属涂层，去除部件非接触区域中的金属涂层， 在组件的边缘区域上施加周围环境，将晶片布置在由夹紧环保持的箔上，将由箔承载的晶片化合物的组分彼此分离，将覆盖掩模布置在由 不要被涂覆的箔，在被掩模覆盖的单独部件上施加金属涂层，去除掩模，以及从箔中去除组分并进一步处理单独的部件，其中在单独的部件上施加金属涂层 掩模覆盖的部件通过热喷涂进行。

公开(公告)号：US20140017854A1

公开(公告)日：2014-01-16

申请号：US14030058

申请日：2013-09-18

Applicant: XINTEC INC.

Inventor： Ching-Yu NI ,  Chang-Sheng HSU

IPC: H01L21/78

CPC classification number: H01L21/78 ,  B81B7/0051 ,  B81C2203/0118 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/585 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/2732 ,  H01L2224/27618 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.

Abstract translation: 根据本发明的实施例提供了芯片封装及其制造方法。 芯片封装包含具有芯片的半导体衬底。 封装层设置在半导体衬底上。 间隔件设置在半导体衬底和封装层之间，其中由半导体衬底，间隔件和封装层组成的侧表面具有凹部。 该方法包括在半导体晶片的多个芯片和封装层之间形成多个间隔物，其中对应于每个芯片的每个间隔件彼此分离，并且间隔件从芯片的边缘向内收缩以形成凹部 并且沿着任何两个相邻芯片之间的划线切割半导体晶片以形成多个芯片封装。