公开(公告)号：US20180061806A1

公开(公告)日：2018-03-01

申请号：US15686584

申请日：2017-08-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  OhHan Kim ,  InSang Yoon

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L24/96 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/95001 ,  H01L2224/95136 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces.

公开(公告)号：US09583450B2

公开(公告)日：2017-02-28

申请号：US14886567

申请日：2015-10-19

Applicant: PLAYNITRIDE INC.

Inventor： Yu-Chu Li ,  Yu-Hung Lai ,  Tzu-Yang Lin

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L24/00 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/83 ,  H01L24/95 ,  H01L24/97 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/83005 ,  H01L2224/83097 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/95001 ,  H01L2224/951 ,  H01L2224/95136 ,  H01L2224/97 ,  H01L2933/0033 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2924/01049

Abstract: A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a supporting substrate and a plurality of light-emitting elements, each of the light-emitting elements being removably connected to the supporting substrate and having a surface opposite to the supporting substrate; disposing the light-emitting unit spacingly above a package substrate in such a manner that the surface of each of the light-emitting elements faces the package substrate; and disconnecting the light-emitting elements from the supporting substrate to allow the light-emitting elements to fall onto the package substrate by gravity, so as to connect the light-emitting elements with the package substrate in a non-contact transferring method.

Abstract translation: 将发光元件转印到封装基板上的方法包括：提供包括支撑基板和多个发光元件的发光单元，每个发光元件可移除地连接到支撑基板，并且具有 表面与支撑基板相对; 以这样的方式将发光单元间隔地设置在封装基板上，使得每个发光元件的表面面向封装基板; 并且将发光元件从支撑基板上断开以允许发光元件通过重力落在封装基板上，从而以非接触转印方法将发光元件与封装基板连接。

公开(公告)号：US20170036342A1

公开(公告)日：2017-02-09

申请号：US14816060

申请日：2015-08-03

Applicant: MIKRO MESA TECHNOLOGY CO., LTD.

Inventor： Li-Yi CHEN ,  Pei-Yu CHANG ,  Chih-Hui CHAN ,  Chun-Yi CHANG ,  Shih-Chyn LIN ,  Hsin-Wei LEE

IPC: B25J7/00 ,  H01L21/683 ,  B25J15/00

CPC classification number: B25J7/00 ,  B25J15/0052 ,  B25J15/008 ,  B25J15/0085 ,  H01L21/6833 ,  H01L21/6835 ,  H01L24/75 ,  H01L24/95 ,  H01L24/97 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2224/75303 ,  H01L2224/7531 ,  H01L2224/75312 ,  H01L2224/75315 ,  H01L2224/75725 ,  H01L2224/7598 ,  H01L2224/95001 ,  H01L2224/95136

Abstract: A transfer head array includes a body and a plurality of transfer heads. The body has a first surface, a second surface opposite to the first surface, and a plurality of recesses. The first surface has at least one chucking region and at least one interference avoidance region, and the recesses are separated from each other and are disposed in the interference avoidance region. The transfer heads are disposed on the chucking region.

Abstract translation: 转印头阵列包括主体和多个转印头。 主体具有第一表面，与第一表面相对的第二表面和多个凹部。 第一表面具有至少一个夹持区域和至少一个干涉避免区域，并且凹部彼此分离并且设置在避免干扰区域中。 转印头位于夹紧区域上。

公开(公告)号：US09412912B2

公开(公告)日：2016-08-09

申请号：US14952227

申请日：2015-11-25

Applicant: PLAYNITRIDE INC.

Inventor： Ching-Liang Lin ,  Yu-Hung Lai ,  Tzu-Yang Lin ,  Pei-Hsin Chen

IPC: H01L21/00 ,  H01L33/48 ,  H01L23/00 ,  H01L25/075 ,  H01L33/62 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L24/83 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0753 ,  H01L33/0095 ,  H01L33/62 ,  H01L2221/68354 ,  H01L2221/68381 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/83001 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/95085 ,  H01L2224/95136 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2924/01032 ,  H01L2924/01049

Abstract: A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a temporary substrate and light-emitting elements; disconnecting the light-emitting elements from the temporary substrate to allow the light-emitting elements to float on a fluid; adjusting spacings between the light-emitting elements to have a predetermined size by controlling flow of the fluid; placing a package substrate into the fluid, followed by aligning the light-emitting elements with connecting pads of the package substrate so as to correspondingly place the light-emitting elements on the connecting pads; and removing the package substrate with the light-emitting elements from the fluid.

Abstract translation: 将发光元件转印到封装衬底上的方法包括：提供包括临时衬底和发光元件的发光单元; 将发光元件与临时衬底断开以允许发光元件漂浮在流体上; 通过控制流体的流动来调节发光元件之间的间隔以具有预定的尺寸; 将封装衬底放置在流体中，然后将发光元件与封装衬底的连接焊盘对准，以便相应地将发光元件放置在连接焊盘上; 以及从所述流体中用所述发光元件去除所述封装衬底。

公开(公告)号：US20160111605A1

公开(公告)日：2016-04-21

申请号：US14886567

申请日：2015-10-19

Applicant: PLAYNITRIDE INC.

Inventor： YU-CHU LI ,  YU-HUNG LAI ,  TZU-YANG LIN

IPC: H01L33/48

CPC classification number: H01L24/00 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/83 ,  H01L24/95 ,  H01L24/97 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/83005 ,  H01L2224/83097 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/95001 ,  H01L2224/951 ,  H01L2224/95136 ,  H01L2224/97 ,  H01L2933/0033 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2924/01049

Abstract: A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a supporting substrate and a plurality of light-emitting elements, each of the light-emitting elements being removably connected to the supporting substrate and having a surface opposite to the supporting substrate; disposing the light-emitting unit spacingly above a package substrate in such a manner that the surface of each of the light-emitting elements faces the package substrate; and disconnecting the light-emitting elements from the supporting substrate to allow the light-emitting elements to fall onto the package substrate by gravity, so as to connect the light-emitting elements with the package substrate in a non-contact transferring method.

Abstract translation: 将发光元件转印到封装基板上的方法包括：提供包括支撑基板和多个发光元件的发光单元，每个发光元件可移除地连接到支撑基板，并且具有 表面与支撑基板相对; 以这样的方式将发光单元间隔地设置在封装基板上，使得每个发光元件的表面面向封装基板; 并且将发光元件从支撑基板上断开以允许发光元件通过重力落在封装基板上，从而以非接触转印方法将发光元件与封装基板连接。

公开(公告)号：US20150155445A1

公开(公告)日：2015-06-04

申请号：US14530230

申请日：2014-10-31

Applicant: Sharp Laboratories of America, Inc.

Inventor： Changqing Zhan ,  Mark Albert Crowder ,  Paul John Schuele

IPC: H01L33/48 ,  H01L33/00

CPC classification number: H01L33/005 ,  H01L24/95 ,  H01L25/0753 ,  H01L33/0095 ,  H01L2224/95085 ,  H01L2224/95136 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2933/0033 ,  H01L2924/00012

Abstract: A fluidic assembly method is provided that uses a counterbore pocket structure. The method is based upon the use of a substrate with a plurality of counterbore pocket structures formed in the top surface, with each counterbore pocket structure having a through-hole to the substrate bottom surface. The method flows an ink with a plurality of objects over the substrate top surface. As noted above, the objects may be micro-objects in the shape of a disk. For example, the substrate may be a transparent substrate and the disks may be light emitting diode (LED) disks. Simultaneously, a suction pressure is created at the substrate bottom surface. In response to the suction pressure from the through-holes, the objects are drawn into the counterbore pocket structures. Also provided is a related fluidic substrate assembly.

Abstract translation: 提供一种使用沉孔袋结构的流体组装方法。 该方法基于使用具有形成在顶表面中的多个沉孔袋结构的基底，每个沉孔袋结构具有到基底底表面的通孔。 该方法将具有多个物体的油墨流过基板顶表面。 如上所述，物体可以是圆盘形状的微型物体。 例如，衬底可以是透明衬底，并且盘可以是发光二极管（LED）盘。 同时，在基板底面产生吸入压力。 响应于来自通孔的吸入压力，物体被吸入沉孔袋结构中。 还提供了相关的流体基底组件。

公开(公告)号：US20140332940A1

公开(公告)日：2014-11-13

申请号：US13932796

申请日：2013-07-01

Applicant: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.

Inventor： Jong Myoung SON

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/4951 ,  H01L23/49548 ,  H01L24/97 ,  H01L2221/68354 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/951 ,  H01L2224/95136 ,  H01L2224/97 ,  H01L2924/07802 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A quad flat no-lead (QFN) integrated circuit package is provided.The QFN integrated circuit package includes an insulating adhesive layer, a semiconductor chip attached to the insulating adhesive layer, and a lead frame bent to be electrically connected to the semiconductor chip and attached to the insulating adhesive layer.The QFN integrated circuit package according the present invention does not use a die paddle and is thus thin. Accordingly, the volume of the package can be minimized.

Abstract translation: 提供四边形无引脚（QFN）集成电路封装。 QFN集成电路封装包括绝缘粘合剂层，连接到绝缘粘合剂层的半导体芯片和弯曲成与半导体芯片电连接并附着到绝缘粘合剂层的引线框架。 根据本发明的QFN集成电路封装不使用裸片，并且因此薄。 因此，可以使包装的体积最小化。

公开(公告)号：US20110300668A1

公开(公告)日：2011-12-08

申请号：US12792565

申请日：2010-06-02

Applicant: Pirooz Parvarandeh

Inventor： Pirooz Parvarandeh

IPC: H01L21/70 ,  H01L21/60

CPC classification number: H01L24/95 ,  H01L21/673 ,  H01L23/13 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68313 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/80006 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/95136 ,  H01L2224/95143 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2224/82

Abstract: An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.

Abstract translation: 组装过程在载体衬底内适当地定位和对准多个第一管芯。 第一模具定位在形成在载体基板中的空腔内。 然后将载体衬底与其中制造的多个第二模具的第二衬底对准。 第一个模具和第二个模具使用不同的技术制造。 使载体基板和第二基板对齐，使第一模具与第二模具对准。 一个或多个第一管芯可以与每个第二管芯对准。 一旦对准，执行晶片接合工艺以将第一管芯连接到第二管芯。 在一些情况下，去除载体衬底，留下第一裸片与第二衬底的第二裸片结合。 在其他情况下，载体基板作为盖留在原位。 然后将第二衬底切割以形成模具堆叠。

公开(公告)号：US20110111559A1

公开(公告)日：2011-05-12

申请号：US13006227

申请日：2011-01-13

Applicant: James G. Mitchell ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

Inventor： James G. Mitchell ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

IPC: H01L21/50

CPC classification number: H01L25/0652 ,  H01L23/10 ,  H01L23/48 ,  H01L24/02 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/73251 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/95136 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72

Abstract: Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.

Abstract translation: 描述了多芯片模块（MCM）的实施例。 该MCM包括第一半导体管芯和第二半导体管芯，其中可以是第一半导体管芯或第二半导体管芯的给定半导体管芯包括靠近给定半导体管芯的表面的接近连接器。 此外，给定的半导体管芯被配置为通过一个或多个接近连接器的接近通信与另一个半导体管芯通信信号。 此外，MCM包括对准板和联接到对准板的顶板。 该对准板包括被配置为容纳第一半导体管芯的第一负特征构件和被配置为容纳第二半导体管芯的第二负特征，并且顶板包括正特征。 注意，正特征耦合到第一半导体管芯，并且正特征有利于第一半导体管芯的机械定位。

公开(公告)号：US07893531B2

公开(公告)日：2011-02-22

申请号：US11864408

申请日：2007-09-28

Applicant: James G. Mitchell ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

Inventor： James G. Mitchell ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

IPC: H01L23/34

CPC classification number: H01L25/0652 ,  H01L23/10 ,  H01L23/48 ,  H01L24/02 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/73251 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/95136 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72

Abstract: Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.