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公开(公告)号：US12128377B2
公开(公告)日：2024-10-29
申请号：US17297923
申请日：2019-11-27
Applicant: MGI Tech Co., Ltd.
Inventor： Liang Wang , Jian Gong , Yan-You Lin , Shifeng Li
CPC classification number: B01J19/0046 , B01L3/502707 , B01L3/502715 , H01L24/32 , H01L24/83 , H01L24/95 , B01J2219/00529 , B01J2219/00662 , B01L2300/0819 , H01L24/73 , H01L2224/32059 , H01L2224/32137 , H01L2224/32155 , H01L2224/32225 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2224/83005 , H01L2224/83136 , H01L2224/83191 , H01L2224/83192 , H01L2224/83951
Abstract: An apparatus (100) including multiple biological chips (110,120) includes a substrate (101), a first adhesive layer (134) disposed on the substrate (101), a first biological chip (110) and a second biological chip (120) disposed on the first adhesive layer (134) and attached to the substrate (101) by the adhesive layer (134). The apparatus (100) further includes a filler (130) disposed between the first biological chip (110) and the second biological chip (120). The filler (130) includes a second adhesive layer (135) extending between a side surface (114) of the first biological chip (110) and a side surface (124) of the second biological chip (120), the second adhesive layer (135) attaching the first biological chip (110) to the second biological chip (120). The filler (130) also includes a surface layer (132) disposed over the second adhesive layer (135). The surface layer (132) has a hydrophobic surface that is co-planar with a top surface (111) of the first biological chip (110) and a top surface (121) of the second biological chip (120).
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公开(公告)号：US20230282612A1
公开(公告)日：2023-09-07
申请号：US18313492
申请日：2023-05-08
Inventor： Ching-Hung Wang , Yeong-Jyh Lin , Ching I Li , Tzu-Wei Yu , Chung-Yi Yu
CPC classification number: H01L24/83 , H01L21/681 , H01L24/98 , H01L2224/8393 , H01L2224/83136
Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes performing a bonding process to bond a first semiconductor substrate to a second semiconductor substrate. A shift measurement process is performed on the first and second semiconductor substrates. The shift measurement process includes moving a plurality of substrate pins from a plurality of initial positions to a plurality of measurement positions. The plurality of substrate pins are disposed outside of perimeters of the first and second semiconductor substrates. A shift value is determined between the first semiconductor substrate and the second semiconductor substrate based at least in part on a difference between the plurality of initial positions and the plurality of measurement positions.
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公开(公告)号：US20180254253A1
公开(公告)日：2018-09-06
申请号：US15973276
申请日：2018-05-07
Applicant: Infineon Technologies AG
Inventor： Xikun Zhang , Dejiang Chang , Bill Agar , Michael Lefevre , Alexander Komposch
IPC: H01L23/66 , H01L23/495 , H01L23/498 , H01L23/00 , H01L25/07 , H01L25/00 , H01L29/16
CPC classification number: H01L23/66 , H01L23/49503 , H01L23/49568 , H01L23/49575 , H01L23/49844 , H01L24/27 , H01L24/32 , H01L24/83 , H01L25/072 , H01L25/50 , H01L29/16 , H01L2223/6644 , H01L2223/6672 , H01L2224/29111 , H01L2224/32245 , H01L2224/83136 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/1033 , H01L2924/13091 , H01L2924/19041
Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.
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公开(公告)号：US09524929B2
公开(公告)日：2016-12-20
申请号：US14499181
申请日：2014-09-28
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Kwang Soo Kim , Joon Seok Chae , Suk Ho Lee
IPC: H01L23/495 , H01L23/538 , H01L25/00 , H01L25/065 , H01L23/433 , H01L23/00
CPC classification number: H01L23/49575 , H01L23/4334 , H01L23/49524 , H01L23/49551 , H01L23/49562 , H01L23/5384 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/92 , H01L25/0655 , H01L25/50 , H01L2224/26135 , H01L2224/26145 , H01L2224/27312 , H01L2224/27334 , H01L2224/29083 , H01L2224/2919 , H01L2224/2929 , H01L2224/29291 , H01L2224/293 , H01L2224/3201 , H01L2224/32145 , H01L2224/32227 , H01L2224/32257 , H01L2224/35847 , H01L2224/37005 , H01L2224/37011 , H01L2224/37013 , H01L2224/37147 , H01L2224/4007 , H01L2224/40105 , H01L2224/40137 , H01L2224/40227 , H01L2224/40499 , H01L2224/40991 , H01L2224/40993 , H01L2224/48091 , H01L2224/48111 , H01L2224/48137 , H01L2224/73215 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/73271 , H01L2224/83007 , H01L2224/831 , H01L2224/83136 , H01L2224/83139 , H01L2224/83447 , H01L2224/83815 , H01L2224/84007 , H01L2224/84136 , H01L2224/84138 , H01L2224/84815 , H01L2224/92157 , H01L2224/92165 , H01L2224/92166 , H01L2224/92246 , H01L2224/92247 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/0665 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/06 , H01L2224/83 , H01L2224/84
Abstract: There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame formed on a top surface of the first semiconductor device and having an inlet formed to inject a solder paste; and spaces inserted between the first semiconductor device and the lead frame to form a separation space, wherein the solder paste is filled in the separation space.
Abstract translation: 提供了一种半导体模块封装，包括：通过在其上安装一个或多个第一半导体器件而形成的基底基板; 引线框架，形成在所述第一半导体器件的顶表面上，并且具有形成为用于注入焊膏的入口; 以及插入在第一半导体器件和引线框架之间的空间以形成分离空间，其中焊膏填充在分离空间中。
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5.发明申请
公开(公告)号：US20160155906A1
公开(公告)日：2016-06-02
申请号：US14952227
申请日：2015-11-25
Applicant: PLAYNITRIDE INC.
Inventor： Ching-Liang LIN , Yu-Hung LAI , Tzu-Yang LIN , Pei-Hsin CHEN
IPC: H01L33/48
CPC classification number: H01L25/50 , H01L21/6835 , H01L24/83 , H01L24/95 , H01L24/97 , H01L25/0753 , H01L33/0095 , H01L33/62 , H01L2221/68354 , H01L2221/68381 , H01L2224/29124 , H01L2224/29144 , H01L2224/83001 , H01L2224/83136 , H01L2224/83143 , H01L2224/83192 , H01L2224/83805 , H01L2224/95085 , H01L2224/95136 , H01L2224/95146 , H01L2224/97 , H01L2224/83 , H01L2924/0105 , H01L2924/01032 , H01L2924/01049
Abstract: A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a temporary substrate and light-emitting elements; disconnecting the light-emitting elements from the temporary substrate to allow the light-emitting elements to float on a fluid; adjusting spacings between the light-emitting elements to have a predetermined size by controlling flow of the fluid; placing a package substrate into the fluid, followed by aligning the light-emitting elements with connecting pads of the package substrate so as to correspondingly place the light-emitting elements on the connecting pads; and removing the package substrate with the light-emitting elements from the fluid.
Abstract translation: 将发光元件转印到封装衬底上的方法包括：提供包括临时衬底和发光元件的发光单元; 将发光元件与临时衬底断开以允许发光元件漂浮在流体上; 通过控制流体的流动来调节发光元件之间的间隔以具有预定的尺寸; 将封装衬底放置在流体中，然后将发光元件与封装衬底的连接焊盘对准，以便相应地将发光元件放置在连接焊盘上; 以及从所述流体中用所述发光元件去除所述封装衬底。
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公开(公告)号：US20150270207A1
公开(公告)日：2015-09-24
申请号：US14499181
申请日：2014-09-28
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Kwang Soo KIM , Joon Seok Chae , Suk Ho Lee
IPC: H01L23/495 , H01L23/00 , H01L25/00 , H01L25/065 , H01L21/768 , H01L23/538
CPC classification number: H01L23/49575 , H01L23/4334 , H01L23/49524 , H01L23/49551 , H01L23/49562 , H01L23/5384 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/92 , H01L25/0655 , H01L25/50 , H01L2224/26135 , H01L2224/26145 , H01L2224/27312 , H01L2224/27334 , H01L2224/29083 , H01L2224/2919 , H01L2224/2929 , H01L2224/29291 , H01L2224/293 , H01L2224/3201 , H01L2224/32145 , H01L2224/32227 , H01L2224/32257 , H01L2224/35847 , H01L2224/37005 , H01L2224/37011 , H01L2224/37013 , H01L2224/37147 , H01L2224/4007 , H01L2224/40105 , H01L2224/40137 , H01L2224/40227 , H01L2224/40499 , H01L2224/40991 , H01L2224/40993 , H01L2224/48091 , H01L2224/48111 , H01L2224/48137 , H01L2224/73215 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/73271 , H01L2224/83007 , H01L2224/831 , H01L2224/83136 , H01L2224/83139 , H01L2224/83447 , H01L2224/83815 , H01L2224/84007 , H01L2224/84136 , H01L2224/84138 , H01L2224/84815 , H01L2224/92157 , H01L2224/92165 , H01L2224/92166 , H01L2224/92246 , H01L2224/92247 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/0665 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/06 , H01L2224/83 , H01L2224/84
Abstract: There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame formed on a top surface of the first semiconductor device and having an inlet formed to inject a solder paste; and spaces inserted between the first semiconductor device and the lead frame to form a separation space, wherein the solder paste is filled in the separation space.
Abstract translation: 提供了一种半导体模块封装，包括：通过在其上安装一个或多个第一半导体器件而形成的基底基板; 引线框架，形成在所述第一半导体器件的顶表面上，并且具有形成为用于注入焊膏的入口; 以及插入在第一半导体器件和引线框架之间的空间以形成分离空间，其中焊膏填充在分离空间中。
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7.发明授权Method for aligning and bonding elements and a device comprising aligned and bonded elements 有权用于对准和结合元件的方法和包括对准和结合元件的装置
公开(公告)号：US08440504B2
公开(公告)日：2013-05-14
申请号：US12864871
申请日：2008-12-29
Applicant: Philippe Soussan , Wouter Ruythooren , Eric Beyne , Koen De Munck
Inventor： Philippe Soussan , Wouter Ruythooren , Eric Beyne , Koen De Munck
IPC: H01L21/44
CPC classification number: H01L24/90 , F16B5/04 , H01H1/04 , H01H11/042 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/13025 , H01L2224/1308 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16146 , H01L2224/16237 , H01L2224/32145 , H01L2224/75 , H01L2224/757 , H01L2224/81136 , H01L2224/81224 , H01L2224/81801 , H01L2224/83136 , H01L2225/06541 , H01L2225/06575 , H01L2225/06589 , H01L2924/00013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01R4/06 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
Abstract: The present invention is related to a method for aligning and bonding a first element (1) and a second element (2), comprising: obtaining a first element (1) having at least one protrusion, the protrusion having a base portion (12) made of a first material and an upper portion (13) made of a second, deformable material, different from the first material; obtaining a second element (2) having a first main surface and second main surface (8) and at least one through-hole between the first and second main surface; placing the first and second element onto each other; receiving in the through-hole of the second element (2) the protrusion of the first element (1), the protrusion being arranged and constructed so as to extend from an opening of the through-hole in the first main surface to a position beyond an opening of the through-hole in the second main surface (8); deforming the deformable portion (13) of the protrusion, such that the deformed portion mechanically fixes the second element (2) on the first element (1).
Abstract translation: 本发明涉及一种用于对准和接合第一元件（1）和第二元件（2）的方法，包括：获得具有至少一个突起的第一元件（1），所述突起具有基部（12） 由与第一材料不同的第二可变形材料制成的第一材料和上部（13）制成; 获得具有第一主表面和第二主表面（8）的第二元件（2）和在第一和第二主表面之间的至少一个通孔; 将第一和第二元件彼此放置; 在所述第二元件（2）的所述通孔中容纳所述第一元件（1）的突起，所述突起被布置和构造成从所述第一主表面中的所述通孔的开口延伸到超出所述第一元件 在第二主表面（8）中的通孔的开口; 使突起的可变形部分（13）变形，使得变形部分将第二元件（2）机械地固定在第一元件（1）上。
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8.发明授权Integrated circuit package system employing a support structure with a recess 有权采用具有凹槽的支撑结构的集成电路封装系统
公开(公告)号：US08422243B2
公开(公告)日：2013-04-16
申请号：US11610401
申请日：2006-12-13
Applicant: Seng Guan Chow , Antonio B. Dimaano, Jr.
Inventor： Seng Guan Chow , Antonio B. Dimaano, Jr.
IPC: H05K7/00
CPC classification number: H01L23/49548 , H01L21/565 , H01L23/49503 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/05554 , H01L2224/32245 , H01L2224/48247 , H01L2224/48253 , H01L2224/48257 , H01L2224/49109 , H01L2224/49171 , H01L2224/73265 , H01L2224/83136 , H01L2224/85 , H01L2924/00014 , H01L2924/01029 , H01L2924/01046 , H01L2924/14 , H01L2924/181 , H01L2924/18301 , H01L2924/19107 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; processing a top edge of the support structure along an outermost periphery thereof, to include a recess for preventing mold bleed, the recess surrounded by the lead finger system; and encapsulating the recess and the electrical interconnect system with an encapsulation material to interlock the encapsulation material.
Abstract translation: 一种集成电路封装系统，包括：提供包括支撑结构和引线指系统的电互连系统; 沿其最外周处理支撑结构的顶部边缘，以包括用于防止模具渗出的凹部，由引线指系统包围的凹部; 并且用封装材料封装所述凹部和所述电互连系统以使所述封装材料互锁。
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公开(公告)号：US08266796B2
公开(公告)日：2012-09-18
申请号：US12153560
申请日：2008-05-21
Applicant: Ji-Yong Park , Kyoung-Sei Choi
Inventor： Ji-Yong Park , Kyoung-Sei Choi
IPC: H01K3/10
CPC classification number: H05K3/243 , H01L23/13 , H01L23/49805 , H01L24/06 , H01L24/09 , H01L24/31 , H01L24/83 , H01L2224/0401 , H01L2224/16 , H01L2224/83136 , H01L2224/83192 , H01L2224/83194 , H01L2224/83203 , H01L2224/83207 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/1517 , H05K1/111 , H05K3/108 , H05K2201/09736 , H05K2201/10674 , H05K2203/0574 , Y02P70/611 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49162 , Y10T29/49165 , Y10T29/49169 , H01L2924/00014
Abstract: Provided is a wiring substrate, a semiconductor device package including the wiring substrate, and methods of fabricating the same. The semiconductor device package may include a wiring substrate which may include a base film. The base film may include a mounting region and a non-mounting region. The wiring substrate may further include first wiring patterns on the non-mounting region and extending into the mounting region, second wiring patterns on the first wiring patterns of the non-mounting region, and an insulating layer on the non-mounting region, and a semiconductor device which may include bonding pads. At least one of side surfaces of the second wiring patterns adjacent to the mounting region may be electrically connected to at least one of the bonding pads of the semiconductor device.
Abstract translation: 提供了布线基板，包括布线基板的半导体器件封装及其制造方法。 半导体器件封装可以包括可以包括基膜的布线基板。 基膜可以包括安装区域和非安装区域。 布线基板还可以包括在非安装区域上并延伸到安装区域中的第一布线图案，非安装区域的第一布线图案上的第二布线图案和非安装区域上的绝缘层， 可以包括接合焊盘的半导体器件。 与安装区域相邻的第二布线图案的至少一个侧表面可以电连接到半导体器件的至少一个接合焊盘。
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10.发明授权Assembly comprising a functional device and a resonator and method of making same 有权组件包括功能器件和谐振器及其制造方法
公开(公告)号：US07967204B2
公开(公告)日：2011-06-28
申请号：US12248020
申请日：2008-10-08
Applicant: Mark A. Hadley , Curt L. Carrender , John Stephen Smith , Gordon S. W. Craig
Inventor： Mark A. Hadley , Curt L. Carrender , John Stephen Smith , Gordon S. W. Craig
IPC: G06K7/08
CPC classification number: G06K19/07718 , G06K19/07749 , G06K19/07752 , G06K19/07756 , H01L23/66 , H01L24/19 , H01L24/24 , H01L24/83 , H01L24/95 , H01L24/97 , H01L25/50 , H01L29/0657 , H01L2223/6677 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/76155 , H01L2224/82102 , H01L2224/83136 , H01L2224/95085 , H01L2224/95122 , H01L2224/95136 , H01L2224/97 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/10158 , H01L2924/14 , H01L2924/15153 , H01L2924/15155 , H01L2924/15157 , H01L2924/15165 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , Y10T29/53178 , H01L2224/82 , H01L2224/83851 , H01L2924/00
Abstract: A Radio Frequency Identification (RFID) device. The RFID device comprises an antenna assembly and a resonator assembly. The antenna assembly comprises a first substrate and an antenna element. The resonator assembly comprises a second substrate having an integrated circuit connected to a resonator loop. The first substrate and the second substrate are attached to one another. The integrated circuit electrically couples to the antenna element without a direct mechanical contact.
Abstract translation: 射频识别（RFID）设备。 RFID设备包括天线组件和谐振器组件。 天线组件包括第一基板和天线元件。 谐振器组件包括具有连接到谐振器回路的集成电路的第二衬底。 第一基板和第二基板彼此附接。 集成电路电耦合到天线元件而不直接机械接触。
