公开(公告)号：US20240063169A1

公开(公告)日：2024-02-22

申请号：US18227202

申请日：2023-07-27

Applicant: Kulicke and Soffa Industries, Inc.

Inventor： Adeel Ahmad Bajwa ,  Thomas J. Colosimo, JR. ,  Matthew B. Wasserman ,  Robert N. Chylak

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L2224/751 ,  H01L2224/81801 ,  H01L2224/81065

Abstract: A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a reducing gas delivery system configured to provide a reducing gas to a bonding area of a bonding system. The bonding system also includes a gas delivery line configured to transport the reducing gas from a reducing gas source to the reducing gas delivery system. At least a portion of the gas delivery line is heated.

公开(公告)号：US11848346B2

公开(公告)日：2023-12-19

申请号：US17162221

申请日：2021-01-29

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Satoru Wakiyama ,  Kan Shimizu ,  Toshihiko Hayashi ,  Takuya Nakamura ,  Naoki Jyo

IPC: H01L23/00 ,  H01L27/146 ,  H01L23/31

CPC classification number: H01L27/14636 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/81 ,  H01L27/14607 ,  H01L27/14634 ,  H01L27/14643 ,  H01L23/3192 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0239 ,  H01L2224/039 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/03616 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05082 ,  H01L2224/05157 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/81011 ,  H01L2224/8114 ,  H01L2224/81022 ,  H01L2224/81065 ,  H01L2224/8182 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2224/05157 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04941 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01049 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/0346 ,  H01L2924/00014 ,  H01L2224/03616 ,  H01L2924/00014 ,  H01L2224/0361 ,  H01L2924/00012 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/81464 ,  H01L2924/00014 ,  H01L2224/81444 ,  H01L2924/00014 ,  H01L2224/81469 ,  H01L2924/00014 ,  H01L2224/039 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0361 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/0239 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.

公开(公告)号：US20180218998A1

公开(公告)日：2018-08-02

申请号：US15937149

申请日：2018-03-27

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13084 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/13684 ,  H01L2224/13686 ,  H01L2224/13805 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16265 ,  H01L2224/16268 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81026 ,  H01L2224/81065 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/83026 ,  H01L2224/83815 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3841 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US09922960B2

公开(公告)日：2018-03-20

申请号：US15196170

申请日：2016-06-29

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Sumihiro Ichikawa

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/119 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83895 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00015 ,  H01L2924/14 ,  H05K3/328 ,  H05K3/368 ,  H05K3/4007 ,  H05K2203/167 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2224/81121 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/034 ,  H01L2224/113 ,  H01L2224/81203 ,  H01L2224/81201 ,  H01L2924/00

Abstract: A packaging structure includes a first substrate including a first metal terminal and a second metal terminal whose height is lower than the height of the first metal terminal; and a second substrate including a third metal terminal and a fourth metal terminal whose height is lower than the height of the third metal terminal, the second substrate being provided on the first substrate, the first metal terminal and the third metal terminal being directly bonded with each other, and the second metal terminal and the fourth metal terminal being bonded via a connection portion.

公开(公告)号：US20170125359A1

公开(公告)日：2017-05-04

申请号：US15299339

申请日：2016-10-20

Applicant: FUJITSU LIMITED

Inventor： Taiji Sakai ,  Seiki Sakuyama ,  Nobuhiro Imaizumi ,  Aki Dote

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/4012 ,  H01L23/538 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/98 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/117 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/14177 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17134 ,  H01L2224/17177 ,  H01L2224/17505 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81065 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/00 ,  H01L2021/60022 ,  H01L2225/06513 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

公开(公告)号：US09437573B2

公开(公告)日：2016-09-06

申请号：US14136977

申请日：2013-12-20

Applicant: Cypress Semiconductor Corporation

Inventor： Naomi Masuda ,  Masataka Hoshino ,  Ryota Fukuyama

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/75252 ,  H01L2224/81054 ,  H01L2224/81065 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83907 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.

Abstract translation: 一种半导体器件，包括第一半导体芯片10，形成在第一半导体芯片10上的第一电极12，安装有第一半导体芯片10的第二半导体芯片20，形成有突起24的第二电极22，其形成 以及与第一电极12和第二电极22接合以覆盖突起24的侧面的至少一部分的焊料凸点14及其制造方法。

公开(公告)号：US20160211242A1

公开(公告)日：2016-07-21

申请号：US14599824

申请日：2015-01-19

Applicant: International Business Machines Corporation

Inventor： Peter A. Gruber ,  Katsuyuki Sakuma ,  Da-Yuan Shih

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0612 ,  H01L2224/065 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/1141 ,  H01L2224/1144 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2224/16012 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81022 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81201 ,  H01L2224/8121 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

公开(公告)号：US08828860B2

公开(公告)日：2014-09-09

申请号：US13600204

申请日：2012-08-30

Applicant: Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

Inventor： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

IPC: H01L21/00

CPC classification number: H05K3/3436 ,  B23K1/0016 ,  B23K3/0638 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11011 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/14 ,  H01L2924/20104 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/35 ,  H05K3/3494 ,  H05K13/0465 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.

Abstract translation: 采用多次注入熔融焊料来形成双层焊料凸点，其外层在比其内部部分更低的温度下熔化。 在倒装芯片组装过程中，回流温度高于外层的熔化温度并低于焊料凸块的内部部分的熔化温度。 由于焊料凸块的内部在回流期间不会塌陷，所以可以在相对低的温度下制造倒装芯片组件并具有高的间隔高度。 具有双重焊料凸块的结构有助于倒装芯片组装。

公开(公告)号：US20140065771A1

公开(公告)日：2014-03-06

申请号：US13600204

申请日：2012-08-30

Applicant: Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

Inventor： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

IPC: H01L21/60

CPC classification number: H05K3/3436 ,  B23K1/0016 ,  B23K3/0638 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11011 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/14 ,  H01L2924/20104 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/35 ,  H05K3/3494 ,  H05K13/0465 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.

公开(公告)号：US08409919B2

公开(公告)日：2013-04-02

申请号：US12882673

申请日：2010-09-15

Applicant: Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

Inventor： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

IPC: H01L21/60

CPC classification number: H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7592 ,  H01L2224/81065 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00

Abstract: According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.

Abstract translation: 根据一个实施例的制造方法，将第一焊料凸块和第二焊料凸块对齐并且彼此接触放置，然后将第一和第二焊料凸块加热至等于或高于 焊料凸起并熔化，由此形成第一焊料凸块和第二焊料凸块的部分连接体。 部分连接体被冷却。 冷却的部分连接体在还原气氛中被加热到等于或高于焊料凸点的熔点的温度，从而通过熔化部分连接体而形成永久性连接体，同时除去存在于表面上的氧化膜 部分连接体。