公开(公告)号：US09824993B2

公开(公告)日：2017-11-21

申请号：US15202700

申请日：2016-07-06

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Sumihiro Ichikawa

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L24/17 ,  H01L23/295 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/11848 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81856 ,  H01L2224/81862 ,  H01L2224/81895 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00015 ,  H01L2924/14 ,  H05K3/305 ,  H05K3/328 ,  H05K3/368 ,  H01L2224/81121 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/034 ,  H01L2224/113 ,  H01L2924/00012 ,  H01L2224/81203 ,  H01L2924/00

Abstract: A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers.

公开(公告)号：US09236360B2

公开(公告)日：2016-01-12

申请号：US13650873

申请日：2012-10-12

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Tai-Hung Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/544 ,  H01L21/683

CPC classification number: H01L24/13 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/11 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/27416 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81424 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00

Abstract: An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles.

Abstract translation: 提供一种IC芯片封装和使用其的芯片上玻璃结构。 IC芯片封装包括具有电路表面的IC芯片和形成在电路表面上的多个铜（Cu）凸块。 此外，可以在电路表面上形成非导电膜（NCF）以覆盖铜凸块。 晶片玻璃结构包括玻璃基板，形成在玻璃基板上的诸如铝（Al）电极的多个电极以及形成在电极上的导电膜。 导电膜含有多个导电颗粒。 当IC芯片封装耦合到玻璃基板时，Cu凸块可以经由导电颗粒耦合到相应的电极。

公开(公告)号：US09142532B2

公开(公告)日：2015-09-22

申请号：US14397038

申请日：2013-04-24

Applicant: Tadatomo Suga ,  BONDTECH CO., LTD.

Inventor： Tadatomo Suga ,  Akira Yamauchi

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  B23K31/02 ,  B23K37/00 ,  B23K37/04 ,  H01L21/66 ,  H01L25/10 ,  H01L23/10 ,  H01L21/683

CPC classification number: H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2101/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.[Solution] A method for bonding plural chips each having a chip-side-bond-surface having metal regions to a substrate having plural bond portions has the step (S1) of subjecting the metal regions of the chip-side-bond-surface to surface activating treatment and hydrophilizing treatment; the step (S2) of subjecting the bond portions of the substrate to surface activating treatment and hydrophilizing treatment; the step (S3) of fitting the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portions of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal regions of the chips into contact with the bond portions of the substrate; and the step (S4) of heating the resultant structure, which includes the substrate, and the chips fitted onto the substrate.

Abstract translation: [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US08946852B2

公开(公告)日：2015-02-03

申请号：US13807210

申请日：2011-06-10

Applicant: Hiroyuki Niwa

Inventor： Hiroyuki Niwa

IPC: G03F7/023 ,  H01L23/00 ,  H01L23/29

CPC classification number: G03F7/0233 ,  C08G73/1042 ,  C08G73/1046 ,  C08G73/106 ,  C08L79/08 ,  G03F7/0226 ,  G03F7/0236 ,  G03F7/038 ,  H01L23/293 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1146 ,  H01L2224/1148 ,  H01L2224/11845 ,  H01L2224/13147 ,  H01L2224/27416 ,  H01L2224/276 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81903 ,  H01L2224/82203 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/351 ,  C08L63/00 ,  C08L33/04 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A photosensitive resin composition contains: (a) an alkali-soluble polyimide; (b) a compound which has two or more epoxy groups and/or oxetanyl groups in each molecule; and (c) a quinonediazide compound. Less than 10 parts by weight of an acrylic resin is contained per 100 parts by weight of the polyimide (a); and the content of the compound (b) is not less than 20 parts by weight per 100 parts by weight of the polyimide (a).

Abstract translation: 感光性树脂组合物含有：（a）碱溶性聚酰亚胺; （b）在每个分子中具有两个或更多个环氧基和/或氧杂环丁烷基的化合物; 和（c）醌二叠氮化合物。 每100重量份的聚酰亚胺（a）含有少于10重量份的丙烯酸树脂; 化合物（b）的含量相对于100重量份聚酰亚胺（a）为20重量份以上。

公开(公告)号：US20140170813A1

公开(公告)日：2014-06-19

申请号：US14094431

申请日：2013-12-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ,  IMEC

Inventor： Yu-Hsiang Hu ,  Chung-Shi Liu

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81012 ,  H01L2224/81047 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8183 ,  H01L2224/81948 ,  H01L2224/81986 ,  H01L2224/83047 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9221 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05552

Abstract: A method is provided for bonding a first semiconductor substrate to a second semiconductor substrate using low temperature thermo-compression. The bonding method comprises the step of in-situ mechanically scrubbing the metal contact structure surfaces prior to thermo-compression bonding step, thereby planarizing the removing the oxides and/or contaminants from the metal contact structure surfaces. The thermo-compression bonding step is followed by a thermal annealing step for creating interface diffusion between the metal contact structure of the first and second semiconductor substrates

Abstract translation: 提供了一种使用低温热压将第一半导体衬底接合到第二半导体衬底的方法。 接合方法包括在热压接步骤之前对金属接触结构表面进行原位机械洗涤的步骤，从而平坦化从金属接触结构表面去除氧化物和/或污染物。 热压接步骤之后是用于在第一和第二半导体衬底的金属接触结构之间产生界面扩散的热退火步骤。

公开(公告)号：US20130214379A1

公开(公告)日：2013-08-22

申请号：US13807210

申请日：2011-06-10

Applicant: Hiroyuki Niwa

Inventor： Hiroyuki Niwa

IPC: G03F7/023 ,  H01L23/00 ,  H01L23/29

CPC classification number: G03F7/0233 ,  C08G73/1042 ,  C08G73/1046 ,  C08G73/106 ,  C08L79/08 ,  G03F7/0226 ,  G03F7/0236 ,  G03F7/038 ,  H01L23/293 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1146 ,  H01L2224/1148 ,  H01L2224/11845 ,  H01L2224/13147 ,  H01L2224/27416 ,  H01L2224/276 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81903 ,  H01L2224/82203 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/351 ,  C08L63/00 ,  C08L33/04 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A photosensitive resin composition contains: (a) an alkali-soluble polyimide; (b) a compound which has two or more epoxy groups and/or oxetanyl groups in each molecule; and (c) a quinonediazide compound. Less than 10 parts by weight of an acrylic resin is contained per 100 parts by weight of the polyimide (a); and the content of the compound (b) is not less than 20 parts by weight per 100 parts by weight of the polyimide (a).

Abstract translation: 感光性树脂组合物含有：（a）碱溶性聚酰亚胺; （b）在每个分子中具有两个或更多个环氧基和/或氧杂环丁烷基的化合物; 和（c）醌二叠氮化合物。 每100重量份的聚酰亚胺（a）含有少于10重量份的丙烯酸树脂; 化合物（b）的含量相对于100重量份聚酰亚胺（a）为20重量份以上。

公开(公告)号：US20110254152A1

公开(公告)日：2011-10-20

申请号：US13089449

申请日：2011-04-19

Applicant: Ching-San Lin

Inventor： Ching-San Lin

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/11831 ,  H01L2224/11845 ,  H01L2224/13076 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/13553 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area.

Abstract translation: 提供一种IC芯片及其IC芯片的制造方法。 IC芯片具有芯片体和至少一个凸块。 芯片本体在其表面上具有至少一个导电区域。 凸块形成在芯片体的导电区域上。 凸块包括多个突起和至少一个导电材料。 突起从导电区域突出并且彼此间隔开。 导电材料覆盖突起并电连接导电区域。 该方法包括：（A）提供其表面上具有导电区域的芯片体; （B）在所述芯片体上形成多个突起，其中所述突起从所述导电区域突出并且彼此间隔开; 和（C）形成至少一种导电材料，其中所述导电材料覆盖所述突起并且电连接所述导电区域。

公开(公告)号：US12113042B2

公开(公告)日：2024-10-08

申请号：US17450104

申请日：2021-10-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Liang Lu ,  Wei-Lin Chen ,  Chun-Hao Chou ,  Kuo-Cheng Lee

IPC: H01L23/00

CPC classification number: H01L24/73 ,  H01L24/11 ,  H01L24/17 ,  H01L2224/11466 ,  H01L2224/11845 ,  H01L2224/1703 ,  H01L2224/73104 ,  H01L2224/9211

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

公开(公告)号：US20240088072A1

公开(公告)日：2024-03-14

申请号：US17943580

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： Tsung Han Chiang ,  Shin Yueh Yang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11462 ,  H01L2224/11831 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2924/1436 ,  H01L2924/35121

Abstract: Methods, apparatuses, and systems related to embedded metal pads are described. An example semiconductor device includes a dielectric material, a metal pad having side surface, where a lower portion of the side surface is embedded in the dielectric material, a mask material on a portion of a surface of the dielectric material, an upper portion of the side surface of the metal pad, and a portion of a top surface of the metal pad and a contact pillar on a second portion of the top surface of metal pad, the contact pillar comprising a metal pillar and a pillar bump.

公开(公告)号：US20190252339A1

公开(公告)日：2019-08-15

申请号：US16396782

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ai-Tee Ang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/1191 ,  H01L2224/18 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2224/95001

Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.