公开(公告)号：US11581261B2

公开(公告)日：2023-02-14

申请号：US17186005

申请日：2021-02-26

Applicant: Novatek Microelectronics Corp.

Inventor： Chun-Yu Liao ,  Teng-Jui Yu ,  Jr-Ching Lin ,  Wen-Ching Huang ,  Tai-Hung Lin

IPC: H01L23/52 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

公开(公告)号：US11569162B2

公开(公告)日：2023-01-31

申请号：US16988741

申请日：2020-08-10

Applicant: Novatek Microelectronics Corp.

Inventor： Chiao-Ling Huang ,  Tai-Hung Lin

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/12

Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.

公开(公告)号：US20170162487A1

公开(公告)日：2017-06-08

申请号：US15336821

申请日：2016-10-28

Applicant: Novatek Microelectronics Corp.

Inventor： Wen-Ching Huang ,  Tai-Hung Lin

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49572 ,  H01L21/4882 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3164 ,  H01L23/36 ,  H01L23/49568 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2924/15192

Abstract: A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first surface and having a chip length along a first axis of the chip. The heat-dissipation sheet includes a covering portion and a first extending portion connected to the covering portion and attached to first surface. The covering portion at least partially covers the chip and having a first length along the first axis. The first extending portion has a second length along the first axis substantially longer than the first length of the covering portion, and the covering portion exposes a side surface of the chip, wherein the side surface connects a top surface and a bottom surface of the chip.

公开(公告)号：US20150287686A1

公开(公告)日：2015-10-08

申请号：US14740286

申请日：2015-06-16

Applicant: Novatek Microelectronics Corp.

Inventor： Jung-Fu Hsu ,  Tai-Hung Lin ,  Chang-Tien Tsai

IPC: H01L23/00 ,  H01L27/02

CPC classification number: H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0248 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05088 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/2064 ,  H01L2924/30205 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/43

Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.

Abstract translation: 提供了包括半导体衬底，第一焊盘结构，第二接合焊盘结构和内部接合线的集成电路器件。 第一焊盘结构设置在半导体衬底的表面上并暴露在半导体衬底的外部。 第二焊盘结构设置在半导体衬底的表面上并暴露在半导体衬底的外部。 第一焊盘结构通过内部接合线电耦合到第二接合焊盘结构。 具有更好的电气性能的集成电路器件通过消除电源轨迹或接地轨迹中的内部电阻下降以及提高集成电路器件的信号完整性来提供。

公开(公告)号：US20210183781A1

公开(公告)日：2021-06-17

申请号：US17186005

申请日：2021-02-26

Applicant: Novatek Microelectronics Corp.

Inventor： Chun-Yu Liao ,  Teng-Jui Yu ,  Jr-Ching Lin ,  Wen-Ching Huang ,  Tai-Hung Lin

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

公开(公告)号：US20150069602A1

公开(公告)日：2015-03-12

申请号：US14549551

申请日：2014-11-21

Applicant: Novatek Microelectronics Corp.

Inventor： Chiao-Ling Huang ,  Tai-Hung Lin

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/061 ,  H01L2224/06153 ,  H01L2224/13008 ,  H01L2224/13016 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/13144 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29082 ,  H01L2224/29166 ,  H01L2224/29184 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A chip-on-film device including a flexible circuit film having a wire, a passivation layer having a hole, an adhesive layer, a first pad, a second pad, an interconnection, and a bump is provided. A part of the adhesive layer is disposed in the hole. The first pad and the second pad are disposed under the passivation layer.A part of the interconnection is disposed under the passivation layer, and disposed between the first pad and the second pad. The bump is electrically connected to the first pad via the adhesive layer. The bump is welded on the wire. A part of a first part of the bump overlaps the first pad, a second part of the bump extends to an outside of the pad and at least partially overlaps the interconnection, and the third part of the bump overlaps the second pad.

Abstract translation: 提供了一种片上电影装置，其包括具有导线的柔性电路膜，具有孔的钝化层，粘合剂层，第一焊盘，第二焊盘，互连和凸块。 粘合剂层的一部分设置在孔中。 第一焊盘和第二焊盘设置在钝化层的下方。 互连的一部分设置在钝化层下方，并且设置在第一焊盘和第二焊盘之间。 凸块通过粘合剂层电连接到第一焊盘。 凸块焊接在电线上。 凸块的第一部分的一部分与第一焊盘重叠，凸块的第二部分延伸到焊盘的外部并且至少部分地与互连重叠，并且凸块的第三部分与第二焊盘重叠。

公开(公告)号：US20130292819A1

公开(公告)日：2013-11-07

申请号：US13659932

申请日：2012-10-25

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chiao-Ling Huang ,  Tai-Hung Lin

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/061 ,  H01L2224/06153 ,  H01L2224/13008 ,  H01L2224/13016 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/13144 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29082 ,  H01L2224/29166 ,  H01L2224/29184 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A chip-on-film device including a flexible circuit film having a wire, a passivation layer having a hole, an adhesive layer, a pad, an interconnection, and a bump is provided. A part of the adhesive layer is disposed in the hole. The pad is disposed under the passivation layer, and a part of the pad is disposed under the hole. A part of the interconnection is disposed under the passivation layer, and disposed at a side of the pad, wherein the interconnection does not touch the pad. A part of the bump is disposed on the adhesive layer. The bump is electrically connected to the pad via the adhesive layer. The bump is welded on the wire. A part of a first part of the bump overlaps the pad, and a second part of the bump extends to an outside of the pad and at least partially overlaps the interconnection.

Abstract translation: 提供了一种包括具有线的柔性电路膜，具有孔的钝化层，粘合剂层，衬垫，互连和凸块的片上电影设备。 粘合剂层的一部分设置在孔中。 焊盘设置在钝化层下方，并且焊盘的一部分设置在孔的下方。 互连的一部分设置在钝化层下方，并且设置在焊盘的一侧，其中互连不接触焊盘。 凸块的一部分设置在粘合剂层上。 凸块通过粘合剂层电连接到焊盘。 凸块焊接在电线上。 凸块的第一部分的一部分与焊盘重叠，并且凸块的第二部分延伸到焊盘的外部并且至少部分地重叠互连。

公开(公告)号：US20130093081A1

公开(公告)日：2013-04-18

申请号：US13650873

申请日：2012-10-12

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Tai-Hung Lin

IPC: H01L23/50

CPC classification number: H01L24/13 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/11 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/27416 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81424 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00

Abstract: An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles.

Abstract translation: 提供一种IC芯片封装和使用其的芯片上玻璃结构。 IC芯片封装包括具有电路表面的IC芯片和形成在电路表面上的多个铜（Cu）凸块。 此外，可以在电路表面上形成非导电膜（NCF）以覆盖铜凸块。 晶片玻璃结构包括玻璃基板，形成在玻璃基板上的诸如铝（Al）电极的多个电极以及形成在电极上的导电膜。 导电膜含有多个导电颗粒。 当IC芯片封装耦合到玻璃基板时，Cu凸块可以经由导电颗粒耦合到相应的电极。

公开(公告)号：US11515239B2

公开(公告)日：2022-11-29

申请号：US17169553

申请日：2021-02-08

Applicant: Novatek Microelectronics Corp.

Inventor： Hong-Dyi Chang ,  Tai-Hung Lin ,  Jhih-Siou Cheng

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.

公开(公告)号：US20220020673A1

公开(公告)日：2022-01-20

申请号：US17169553

申请日：2021-02-08

Applicant: Novatek Microelectronics Corp.

Inventor： Hong-Dyi Chang ,  Tai-Hung Lin ,  Jhih-Siou Cheng

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.