公开(公告)号：US20220028775A1

公开(公告)日：2022-01-27

申请号：US16934016

申请日：2020-07-21

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Hong-Dyi Chang ,  Chun-Wei Kang ,  Chun-Fu Lin ,  Ju-Lin Huang

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18

Abstract: An integrated circuit package, a die carrier, and a die are provided. The die carrier includes at least one die pad and a plurality of leads. The at least one die pad is suitable for carrying the die. The leads surround the at least one die pad. The leads are disposed on four sides of the die carrier. A length of a long side among the four sides is twice or more a length of a short side among the four sides. The die carrier is suitable for a QFN package or a QFP package.

公开(公告)号：US11244891B1

公开(公告)日：2022-02-08

申请号：US16934016

申请日：2020-07-21

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Hong-Dyi Chang ,  Chun-Wei Kang ,  Chun-Fu Lin ,  Ju-Lin Huang

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L25/16

Abstract: An integrated circuit package, a die carrier, and a die are provided. The die carrier includes at least one die pad and a plurality of leads. The at least one die pad is suitable for carrying the die. The leads surround the at least one die pad. The leads are disposed on four sides of the die carrier. A length of a long side among the four sides is twice or more a length of a short side among the four sides. The die carrier is suitable for a QFN package or a QFP package.

公开(公告)号：US11515239B2

公开(公告)日：2022-11-29

申请号：US17169553

申请日：2021-02-08

Applicant: Novatek Microelectronics Corp.

Inventor： Hong-Dyi Chang ,  Tai-Hung Lin ,  Jhih-Siou Cheng

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.

公开(公告)号：US20220020673A1

公开(公告)日：2022-01-20

申请号：US17169553

申请日：2021-02-08

Applicant: Novatek Microelectronics Corp.

Inventor： Hong-Dyi Chang ,  Tai-Hung Lin ,  Jhih-Siou Cheng

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.